From 5838ed7290461a253587d854226758b84afbb54d Mon Sep 17 00:00:00 2001
From: Brad Beckmann <Brad.Beckmann@amd.com>
Date: Fri, 6 Apr 2012 13:47:07 -0700
Subject: MOESI_hammer: tbe allocation and dependent wakeup fixes
---
src/mem/protocol/MOESI_hammer-cache.sm | 29 +++++++++++++++++++++++++----
src/mem/protocol/MOESI_hammer-dir.sm | 4 ++++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 219096d26..1fe353ce5 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -1481,6 +1481,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
transition(SR, {Load, Ifetch}, S) {
h_load_hit;
k_popMandatoryQueue;
+ ka_wakeUpAllDependents;
}
transition({S, SR}, Store, SM) {
@@ -1525,6 +1526,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
transition(OR, {Load, Ifetch}, O) {
h_load_hit;
k_popMandatoryQueue;
+ ka_wakeUpAllDependents;
}
transition({O, OR}, Store, OM) {
@@ -1569,14 +1571,26 @@ machine(L1Cache, "AMD Hammer-like protocol")
}
// Transitions from Modified
- transition({MM, MMR}, {Load, Ifetch}, MM) {
+ transition({MM, M}, {Load, Ifetch}) {
+ h_load_hit;
+ k_popMandatoryQueue;
+ }
+
+ transition(MM, Store) {
+ hh_store_hit;
+ k_popMandatoryQueue;
+ }
+
+ transition(MMR, {Load, Ifetch}, MM) {
h_load_hit;
k_popMandatoryQueue;
+ ka_wakeUpAllDependents;
}
- transition({MM, MMR}, Store, MM) {
+ transition(MMR, Store, MM) {
hh_store_hit;
k_popMandatoryQueue;
+ ka_wakeUpAllDependents;
}
transition({MM, M, MMR, MR}, Flush_line, MM_F) {
@@ -1630,14 +1644,21 @@ machine(L1Cache, "AMD Hammer-like protocol")
}
// Transitions from Dirty Exclusive
- transition({M, MR}, {Load, Ifetch}, M) {
+ transition(M, Store, MM) {
+ hh_store_hit;
+ k_popMandatoryQueue;
+ }
+
+ transition(MR, {Load, Ifetch}, M) {
h_load_hit;
k_popMandatoryQueue;
+ ka_wakeUpAllDependents;
}
- transition({M, MR}, Store, MM) {
+ transition(MR, Store, MM) {
hh_store_hit;
k_popMandatoryQueue;
+ ka_wakeUpAllDependents;
}
transition(M, L2_Replacement, MI) {
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 24d64349e..1fc946386 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -542,6 +542,7 @@ machine(Directory, "AMD Hammer-like protocol")
}
action(v_allocateTBE, "v", desc="Allocate TBE") {
+ check_allocate(TBEs);
peek(requestQueue_in, RequestMsg) {
TBEs.allocate(address);
set_tbe(TBEs[address]);
@@ -551,6 +552,7 @@ machine(Directory, "AMD Hammer-like protocol")
}
action(vd_allocateDmaRequestInTBE, "vd", desc="Record Data in TBE") {
+ check_allocate(TBEs);
peek(dmaRequestQueue_in, DMARequestMsg) {
TBEs.allocate(address);
set_tbe(TBEs[address]);
@@ -1258,6 +1260,8 @@ machine(Directory, "AMD Hammer-like protocol")
peek(unblockNetwork_in, ResponseMsg) {
assert(in_msg.Dirty == false);
assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
+ DPRINTF(RubySlicc, "%s\n", in_msg.DataBlk);
+ DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
// NOTE: The following check would not be valid in a real
// implementation. We include the data in the "dataless"
--
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