From 60454042aaf1c5b3380536c4a1d2255d8f648d7d Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 26 Jun 2006 17:50:48 -0400 Subject: don't depend on the memory system to return the atomic cpu a multiple of cpu cycles. --HG-- extra : convert_revision : e5eb36f14c8394381a0269fefd34a178833c8346 --- src/cpu/simple/atomic.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 071193f02..ce28ba9c8 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -410,15 +410,14 @@ AtomicSimpleCPU::tick() postExecute(); if (simulate_stalls) { - // This calculation assumes that the icache and dcache - // access latencies are always a multiple of the CPU's - // cycle time. If not, the next tick event may get - // scheduled at a non-integer multiple of the CPU - // cycle time. Tick icache_stall = icache_latency - cycles(1); Tick dcache_stall = dcache_access ? dcache_latency - cycles(1) : 0; - latency += icache_stall + dcache_stall; + Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); + if (cycles(stall_cycles) < (icache_stall + dcache_stall)) + latency += cycles(stall_cycles+1); + else + latency += cycles(stall_cycles); } } -- cgit v1.2.3