From 0b0d5a282a25a936d4aa92ec81ef2bd50141ce03 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 11:33:44 -0500 Subject: Draining fixes. src/cpu/o3/cpu.cc: Handle draining properly when CPU isn't actually being used. src/cpu/simple/atomic.cc: Be sure to set status properly when draining. src/mem/bus.cc: Fix for draining. --HG-- extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f --- src/cpu/o3/cpu.cc | 6 ++++++ src/cpu/simple/atomic.cc | 3 +++ src/mem/bus.cc | 5 ++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index dfe42d882..580816372 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -819,6 +819,12 @@ unsigned int FullO3CPU::drain(Event *drain_event) { DPRINTF(O3CPU, "Switching out\n"); + + // If the CPU isn't doing anything, then return immediately. + if (_status == Idle || _status == SwitchedOut) { + return 0; + } + drainCount = 0; fetch.drain(); decode.drain(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 4f68cfd6f..f94ea0917 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -213,6 +213,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) break; } } + if (_status != Running) { + _status = Idle; + } } diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 7b65d252b..ae87d8099 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -242,8 +242,11 @@ Bus::recvRetry(int id) } } //If we weren't able to drain before, we might be able to now. - if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) + if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) { drainEvent->process(); + // Clear the drain event once we're done with it. + drainEvent = NULL; + } } Port * -- cgit v1.2.3 From 21f43bfc4b01051e688a4eec4ce5aef12ad2c951 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 11:37:26 -0500 Subject: Be sure to populate the packet's finishTime field in the atomic timing case. --HG-- extra : convert_revision : ef34818eb2dea5b3a8e754bf56745a7cd2497bf0 --- src/mem/bus.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mem/bus.cc b/src/mem/bus.cc index ae87d8099..8ea67a0e4 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -370,6 +370,10 @@ Bus::recvAtomic(PacketPtr pkt) DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); assert(pkt->getDest() == Packet::Broadcast); + + // Assume one bus cycle in order to get through. This may have + // some clock skew issues yet again... + pkt->finishTime = curTick + clock; Tick snoopTime = atomicSnoop(pkt); if (snoopTime) return snoopTime; //Snoop satisfies it -- cgit v1.2.3 From 0ba2cc6571f80beb3600000649403cbff0b67d8b Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 15:05:13 -0500 Subject: Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches. configs/common/Simulation.py: Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU. However the O3CPU must always use caches, so a check for that must still exist. Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU. configs/example/fs.py: configs/example/se.py: Atomic CPU now handles caches. --HG-- extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e --- configs/common/Simulation.py | 16 ++++------------ configs/example/fs.py | 2 +- configs/example/se.py | 2 +- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index d88373d54..f43fa9a6f 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -84,10 +84,6 @@ def run(options, root, testsys, cpu_class): if not m5.build_env['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] @@ -107,19 +103,15 @@ def run(options, root, testsys, cpu_class): switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) - else: + if not options.caches: # O3 CPU must have a cache to work. switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus_1[i].connectMemPorts(testsys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus_1 = switch_cpus_1 + testsys.switch_cpus = switch_cpus + testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] @@ -222,5 +214,5 @@ def run(options, root, testsys, cpu_class): if exit_cause == '': exit_cause = exit_event.getCause() - print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) diff --git a/configs/example/fs.py b/configs/example/fs.py index 180cd2719..a9f1d579a 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -95,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) np = options.num_cpus test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] for i in xrange(np): - if options.caches and not options.standard_switch and not FutureClass: + if options.caches: test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) test_sys.cpu[i].connectMemPorts(test_sys.membus) diff --git a/configs/example/se.py b/configs/example/se.py index 0a158244f..0944a030e 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -101,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], system.physmem.port = system.membus.port for i in xrange(np): - if options.caches and not options.standard_switch and not FutureClass: + if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) system.cpu[i].connectMemPorts(system.membus) -- cgit v1.2.3