From 6eebfda2d9a4613d8357a2f266289311240a0a1b Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Wed, 16 Aug 2006 23:46:54 -0400
Subject: Fix the caches not working in the regression

src/python/m5/objects/BaseCPU.py:
    Make mem parameter a MemObject, not just a PhysicalMemory
    Fix a reference not using self
tests/configs/simple-atomic.py:
    Set the mem paramter
tests/configs/simple-timing.py:
    Set the mem parameter

--HG--
extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
---
 src/python/m5/objects/BaseCPU.py | 5 +++--
 tests/configs/simple-atomic.py   | 1 +
 tests/configs/simple-timing.py   | 2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 7906156a2..88a8bf5e3 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -6,7 +6,7 @@ from Bus import Bus
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
-    mem = Param.PhysicalMemory(Parent.any, "memory")
+    mem = Param.MemObject(Parent.any, "memory")
 
     system = Param.System(Parent.any, "system object")
     if build_env['FULL_SYSTEM']:
@@ -43,11 +43,12 @@ class BaseCPU(SimObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+#        self.mem = dc
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
         self.addPrivateSplitL1Caches(ic, dc)
         self.toL2Bus = Bus()
         self.connectMemPorts(self.toL2Bus)
         self.l2cache = l2c
-        self.l2cache.cpu_side = toL2Bus.port
+        self.l2cache.cpu_side = self.toL2Bus.port
         self._mem_ports = ['l2cache.mem_side']
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 9b7ce1429..2bf67f3b1 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(),
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
+system.cpu.mem = system.physmem
 
 root = Root(system = system)
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 823a8aec1..78dfabe3b 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,7 +39,7 @@ class MyCache(BaseCache):
 cpu = TimingSimpleCPU()
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
-
+cpu.mem = cpu.dcache
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
-- 
cgit v1.2.3


From 825a7aadd24493e4cdf9590434134a31a8548cbe Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 21 Aug 2006 13:16:46 -0400
Subject: Changes so that time in the packet is actually set properly.

src/mem/packet.hh:
    Make sure packets set the time parameter correctly.

--HG--
extra : convert_revision : e381d2789e0aaa1b6c2fbde417b7ba5815deec61
---
 src/mem/packet.hh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index c8b0cdaed..a88c78a78 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -266,6 +266,7 @@ class Packet
            result(Unknown)
     {
         flags = 0;
+        time = curTick;
     }
 
     /** Alternate constructor if you are trying to create a packet with
@@ -280,6 +281,7 @@ class Packet
            result(Unknown)
     {
         flags = 0;
+        time = curTick;
     }
 
     /** Destructor. */
@@ -295,6 +297,7 @@ class Packet
         assert(req->validPaddr);
         addr = req->paddr;
         size = req->size;
+        time = req->time;
         addrSizeValid = true;
         result = Unknown;
         if (dynamicData) {
-- 
cgit v1.2.3