From 741b24326040cfdd534d05ca46ba4c962bab18f1 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:09 -0500 Subject: ARM: Ignore/warn access to the bpimva registers. --- src/arch/arm/isa/formats/misc.isa | 3 +++ src/arch/arm/miscregs.hh | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 8ba46960a..7d58350a4 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -119,6 +119,9 @@ def format McrMrc15() {{ case MISCREG_ICIMVAU: return new WarnUnimplemented( isRead ? "mrc icimvau" : "mcr icimvau", machInst); + case MISCREG_BPIMVA: + return new WarnUnimplemented( + isRead ? "mrc bpimva" : "mcr bpimva", machInst); default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index df3d00946..d66ce0f78 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -97,6 +97,7 @@ namespace ArmISA MISCREG_ICIALLUIS, MISCREG_ICIALLU, MISCREG_ICIMVAU, + MISCREG_BPIMVA, MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_TCMTR, @@ -136,7 +137,6 @@ namespace ArmISA MISCREG_RGNR, MISCREG_BPIALLIS, MISCREG_BPIALL, - MISCREG_BPIMVA, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_MCCSW, @@ -161,7 +161,7 @@ namespace ArmISA "sctlr", "dccisw", "dccimvac", "dccmvac", "contextidr", "tpidrurw", "tpidruro", "tpidrprw", "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr", - "icialluis", "iciallu", "icimvau", + "icialluis", "iciallu", "icimvau", "bpimva", "ctr", "tcmtr", "mpuir", "mpidr", "midr", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", @@ -170,7 +170,7 @@ namespace ArmISA "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "rgnr", "bpiallis", - "bpiall", "bpimva", "dcimvac", "dcisw", "mccsw", + "bpiall", "dcimvac", "dcisw", "mccsw", "dccmvau", "nop", "raz" }; -- cgit v1.2.3