From 760e2eb6f4e40080a49e6372284c5213bf95475a Mon Sep 17 00:00:00 2001 From: Nikos Nikoleris Date: Tue, 19 Dec 2017 21:43:51 +0000 Subject: arch-arm: Fix cache line size for cache maintenace inst Cache maintenance operations operate on whole cache blocks. This changeset uses the system cache line size as the size of the cache maintenance requests and masks the lower bits of the effective address. Change-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/7824 Maintainer: Andreas Sandberg --- src/arch/arm/isa/templates/misc.isa | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 639ff3aca..6d63b8e14 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013,2017 ARM Limited +// Copyright (c) 2010-2013,2017-2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -646,9 +646,9 @@ def template Mcr15Execute {{ } if (fault == NoFault) { - Addr size = 64; - EA &= ~(size - 1); - fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL); + Addr op_size = xc->tcBase()->getSystemPtr()->cacheLineSize(); + EA &= ~(op_size - 1); + fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL); } } else { xc->setPredicate(false); @@ -675,9 +675,9 @@ def template Mcr15InitiateAcc {{ } if (fault == NoFault) { - Addr size = 64; - EA &= ~(size - 1); - fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL); + Addr op_size = xc->tcBase()->getSystemPtr()->cacheLineSize(); + EA &= ~(op_size - 1); + fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL); } } else { xc->setPredicate(false); -- cgit v1.2.3