From 89f2871168bcd2a69f3edc2e9f12f3bc66101128 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Jan 2018 15:17:08 -0800 Subject: riscv: Add overrides to various StaticInst methods. This makes riscv compile with the version of clang(++) I have on my workstation. Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328 Reviewed-on: https://gem5-review.googlesource.com/7643 Reviewed-by: Jason Lowe-Power Maintainer: Gabe Black --- src/arch/riscv/insts/static_inst.hh | 12 ++++++++---- src/arch/riscv/isa/formats/amo.isa | 14 ++++++++------ src/arch/riscv/isa/formats/basic.isa | 2 +- src/arch/riscv/isa/formats/mem.isa | 7 ++++--- src/arch/riscv/isa/formats/standard.isa | 6 +++--- 5 files changed, 24 insertions(+), 17 deletions(-) diff --git a/src/arch/riscv/insts/static_inst.hh b/src/arch/riscv/insts/static_inst.hh index bf34c9bae..073b60c1c 100644 --- a/src/arch/riscv/insts/static_inst.hh +++ b/src/arch/riscv/insts/static_inst.hh @@ -75,23 +75,27 @@ class RiscvMacroInst : public RiscvStaticInst ~RiscvMacroInst() { microops.clear(); } - StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; } + StaticInstPtr + fetchMicroop(MicroPC upc) const override + { + return microops[upc]; + } Fault - initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const + initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override { panic("Tried to execute a macroop directly!\n"); } Fault completeAcc(PacketPtr pkt, ExecContext *xc, - Trace::InstRecord *traceData) const + Trace::InstRecord *traceData) const override { panic("Tried to execute a macroop directly!\n"); } Fault - execute(ExecContext *xc, Trace::InstRecord *traceData) const + execute(ExecContext *xc, Trace::InstRecord *traceData) const override { panic("Tried to execute a macroop directly!\n"); } diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index e3be23749..1dca57191 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -51,10 +51,11 @@ def template AtomicMemOpDeclare {{ // Constructor %(class_name)sLoad(ExtMachInst machInst, %(class_name)s *_p); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, + Trace::InstRecord *) const override; Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const; + Trace::InstRecord *) const override; }; class %(class_name)sStore : public %(base_class)sMicro @@ -63,10 +64,11 @@ def template AtomicMemOpDeclare {{ // Constructor %(class_name)sStore(ExtMachInst machInst, %(class_name)s *_p); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, + Trace::InstRecord *) const override; Fault completeAcc(PacketPtr, ExecContext *, - Trace::InstRecord *) const; + Trace::InstRecord *) const override; }; }; }}; diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa index bb8401e3d..dd25ba6f7 100644 --- a/src/arch/riscv/isa/formats/basic.isa +++ b/src/arch/riscv/isa/formats/basic.isa @@ -40,7 +40,7 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; using %(base_class)s::generateDisassembly; }; }}; diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index d4c17541a..a932d01cc 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -43,9 +43,10 @@ def template LoadStoreDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index ebe157160..2e0e3edd4 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -43,7 +43,7 @@ def template ImmDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; }; @@ -99,7 +99,7 @@ def template BranchDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; @@ -158,7 +158,7 @@ def template JumpDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; -- cgit v1.2.3