From 96554eca9f7731f6f5e56f9f29c933e230e34bd8 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 29 May 2018 22:09:39 +0100 Subject: arch-arm: Adapting IllegalExecution fault for AArch32 The Illegal Execution fault triggered by the setting of processor state PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED exception fault. We are hence copying the UndefinedInstruction AArch32 fields into the IllegalInstSetStateFault. Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10814 Maintainer: Andreas Sandberg --- src/arch/arm/faults.cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index dd4f9581c..cf58960ec 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -257,6 +257,10 @@ template<> ArmFault::FaultVals ArmFaultVals::vals( "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_INVALID ); +template<> ArmFault::FaultVals ArmFaultVals::vals( + "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, + 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST +); template<> ArmFault::FaultVals ArmFaultVals::vals( // Some dummy values (SupervisorTrap is AArch64-only) "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, @@ -287,11 +291,6 @@ template<> ArmFault::FaultVals ArmFaultVals::vals( "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN ); -template<> ArmFault::FaultVals ArmFaultVals::vals( - // Some dummy values (SPAlignmentFault is AArch64-only) - "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, - 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST -); Addr ArmFault::getVector(ThreadContext *tc) -- cgit v1.2.3