From 9e1fe2050ac55c28b6601770014193321a4013d0 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 12 Oct 2008 20:25:06 -0700
Subject: X86: Let segment manipulation microops be conditional.

---
 src/arch/x86/isa/microops/regop.isa | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index dfb0abeae..4f93fad80 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -978,7 +978,7 @@ let {{
             '''
 
     # Microops for manipulating segmentation registers
-    class SegOp(RegOp):
+    class SegOp(CondRegOp):
         abstract = True
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
             super(SegOp, self).__init__(dest, \
-- 
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