From d7ac2b56c2fdc4a8a5f96ee725f11f37c4432f14 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Tue, 14 Feb 2006 02:03:14 -0500
Subject: make MIPS MT instructions decodable ...

arch/mips/isa/bitfields.isa:
    extra bitfield for decoding

--HG--
extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866
---
 arch/mips/isa/bitfields.isa |  1 +
 arch/mips/isa/decoder.isa   | 82 ++++++++++++++++++++++++++++++++++++++-------
 2 files changed, 70 insertions(+), 13 deletions(-)

diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index 94a8a6467..bead9c151 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -15,6 +15,7 @@ def bitfield RT_HI    <20:19>;
 def bitfield RT_LO    <18:16>;
 
 def bitfield RS	      <25:21>;
+def bitfield RS_MSB   <25:25>;
 def bitfield RS_HI    <25:24>;
 def bitfield RS_LO    <23:21>;
 
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index d6fd90657..2ec7da805 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -229,7 +229,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
                         Rt = xc->miscRegs.cop0[reg_num];
                         }});
 
-                0xC: mtc0({{
+                0x4: mtc0({{
                         //The contents of the coprocessor 0 register specified by the
                         //combination of rd and sel are loaded into general register
                         //rt. Note that not all coprocessor 0 registers support the
@@ -243,6 +243,25 @@ decode OPCODE_HI default FailUnimpl::unknown() {
                         xc->miscRegs.cop0[reg_num] = Rt;
                         }});
 
+                0x8: mftr({{
+                        //The contents of the coprocessor 0 register specified by the
+                        //combination of rd and sel are loaded into general register
+                        //rt. Note that not all coprocessor 0 registers support the
+                        //sel field. In those instances, the sel field must be zero.
+
+                        //MT Code Needed Here
+                        }});
+
+                0xC: mttr({{
+                        //The contents of the coprocessor 0 register specified by the
+                        //combination of rd and sel are loaded into general register
+                        //rt. Note that not all coprocessor 0 registers support the
+                        //sel field. In those instances, the sel field must be zero.
+
+                        //MT Code Needed Here
+                        }});
+
+
                 0xA: rdpgpr({{
                         //Accessing Previous Shadow Set Register Number
                         uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
@@ -252,23 +271,52 @@ decode OPCODE_HI default FailUnimpl::unknown() {
                         }});
             }
 
-          0xB: decode SC {
-            format BasicOp {
-                0x0: di({{
-                        //Accessing Coprocessor 0 "Status" Register
-                        Rt.sw = xc->miscRegs.cop0[12];
-                        xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 0;
+            0xB: decode RD {
+
+                0x0: decode SC {
+                  format BasicOp {
+                    0x0: dvpe({{
+                        Rt.sw = xc->miscRegs.cop0.MVPControl;
+                        xc->miscRegs.cop0.MVPControl[EVP] = 0;
                         }});
 
-                0x1: ei({{
-                        //Accessing Coprocessor 0 "Status" Register
-                        Rt.sw = xc->miscRegs.cop0[12];
-                        xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 1;
+                    0x1: evpe({{
+                        Rt.sw = xc->miscRegs.cop0.MVPControl;
+                        xc->miscRegs.cop0.MVPControl[EVP] = 1;
                         }});
+                  }
+                }
+
+                0x1: decode SC {
+                  format BasicOp {
+                    0x0: dmt({{
+                        Rt.sw = xc->miscRegs.cop0.VPEControl;
+                        xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0;
+                        }});
+
+                    0x1: emt({{
+                        Rt.sw = xc->miscRegs.cop0.VPEControl;
+                        xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1;
+                        }});
+                  }
+                }
+
+                0xC: decode SC {
+                  format BasicOp {
+                    0x0: di({{
+                        Rt.sw = xc->miscRegs.cop0.Status;
+                        xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0;
+                        }});
+
+                    0x1: ei({{
+                        Rt.sw = xc->miscRegs.cop0.Status;
+                        xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1;
+                        }});
+                  }
+                }
             }
-          }
 
-          0xE: BasicOp::wrpgpr({{
+            0xE: BasicOp::wrpgpr({{
                         //Accessing Previous Shadow Set Register Number
                         uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
                         uint64_t reg_num = Rd.uw;
@@ -772,6 +820,14 @@ decode OPCODE_HI default FailUnimpl::unknown() {
                 }
           }
 
+          0x1: decode FUNCTION_LO {
+                format WarnUnimpl {
+                    0x0: fork({{ }});
+                    0x1: yield({{ }});
+                }
+          }
+
+
           //Table A-10 MIPS32 BSHFL Encoding of sa Field
           0x4: decode SA {
 
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