From abbe32b6acacb22761e969b716631c5f616f3229 Mon Sep 17 00:00:00 2001 From: Chuan Zhu Date: Fri, 29 Dec 2017 20:04:14 +0000 Subject: arch-arm: Mask out unsupported trapped exception handling bits Floating-point trapped exception handlings are not currently supported in gem5, therefore the corresponding bits are RAZ/WI in FCPR. Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10045 Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 347e644d1..954375374 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -521,12 +521,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) { const uint32_t ones = (uint32_t)(-1); FPSCR fpscrMask = 0; - fpscrMask.ioe = ones; - fpscrMask.dze = ones; - fpscrMask.ofe = ones; - fpscrMask.ufe = ones; - fpscrMask.ixe = ones; - fpscrMask.ide = ones; fpscrMask.len = ones; fpscrMask.stride = ones; fpscrMask.rMode = ones; @@ -865,12 +859,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) { const uint32_t ones = (uint32_t)(-1); FPSCR fpscrMask = 0; - fpscrMask.ioe = ones; - fpscrMask.dze = ones; - fpscrMask.ofe = ones; - fpscrMask.ufe = ones; - fpscrMask.ixe = ones; - fpscrMask.ide = ones; fpscrMask.len = ones; fpscrMask.stride = ones; fpscrMask.rMode = ones; -- cgit v1.2.3