From b277ad3bdb25e2fe7d53d470a57bf48edb6299df Mon Sep 17 00:00:00 2001 From: Jose Marinho Date: Fri, 28 Jul 2017 15:28:02 +0100 Subject: arch-arm: Only increment SW PMU counters on writes to PMSWINC When writing a bitmask of counters to PMSWINC, the PMU currently increments the corresponding counters regardless of what they are configured to count. According to the ARM ARM (D5.10.4), counters should only be updated if they have been configured to count software events (event type 0). Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9 Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/4285 Reviewed-by: Jason Lowe-Power Maintainer: Andreas Sandberg --- src/arch/arm/pmu.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc index 14b1b50a0..f1ff6cbbc 100644 --- a/src/arch/arm/pmu.cc +++ b/src/arch/arm/pmu.cc @@ -147,8 +147,10 @@ PMU::setMiscReg(int misc_reg, MiscReg val) case MISCREG_PMSWINC: for (int i = 0; i < counters.size(); ++i) { CounterState &ctr(getCounter(i)); - if (ctr.enabled && (val & (1 << i))) + if (ctr.enabled && (val & (1 << i)) + && ctr.eventId == ARCH_EVENT_SW_INCR ) { ++ctr.value; + } } break; -- cgit v1.2.3