From b885dc68a26e0c7a401ca4b338d997ac577847a8 Mon Sep 17 00:00:00 2001 From: Chuan Zhu Date: Mon, 15 Jan 2018 16:14:11 +0000 Subject: arch-arm: Handle route to EL2 in Supervisor Trap Supervisor Trap is supposed to be able to handle exceptions routed to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp() function to Supervisor Trap to handle this, similar to that in UndefinedFault, DataAbort, etc. Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7 Reviewed-by: Jack Travaglini Reviewed-on: https://gem5-review.googlesource.com/7961 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/faults.cc | 31 +++++++++++++++++++++++++++++-- src/arch/arm/faults.hh | 4 +++- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index d143056b1..27894e0c1 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited + * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -923,10 +923,37 @@ SecureMonitorCall::ec(ThreadContext *tc) const return (from64 ? EC_SMC_64 : vals.ec); } +bool +SupervisorTrap::routeToHyp(ThreadContext *tc) const +{ + bool toHyp = false; + + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); + CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); + + // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector + toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); + return toHyp; +} + +uint32_t +SupervisorTrap::iss() const +{ + // If SupervisorTrap is routed to hypervisor, iss field is 0. + if (hypRouted) { + return 0; + } + return issRaw; +} + ExceptionClass SupervisorTrap::ec(ThreadContext *tc) const { - return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; + if (hypRouted) + return EC_UNKNOWN; + else + return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; } ExceptionClass diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index fa6740a1a..bec2c0e8f 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited + * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -335,6 +335,8 @@ class SupervisorTrap : public ArmFaultVals overrideEc(_overrideEc) {} + bool routeToHyp(ThreadContext *tc) const override; + uint32_t iss() const override; ExceptionClass ec(ThreadContext *tc) const override; }; -- cgit v1.2.3