From b94f84196924d60d4d4677929ddb6f677e3d96d9 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 19 Aug 2011 15:08:07 -0500
Subject: ARM: Add support for DIV/SDIV instructions.

---
 src/arch/arm/isa.cc               |  2 +-
 src/arch/arm/isa/formats/mult.isa | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b8a047f65..25bc3161b 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -140,7 +140,7 @@ ISA::clear()
 
     // See section B4.1.84 of ARM ARM
     // All values are latest for ARMv7-A profile
-    miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
+    miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
     miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
     miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
     miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
diff --git a/src/arch/arm/isa/formats/mult.isa b/src/arch/arm/isa/formats/mult.isa
index cfd00b1a5..73157dd57 100644
--- a/src/arch/arm/isa/formats/mult.isa
+++ b/src/arch/arm/isa/formats/mult.isa
@@ -394,6 +394,16 @@ def format ArmSignedMultiplies() {{
                 }
             }
             break;
+          case 0x1:
+            if (op2 == 0 && m == 0 && ra == 0xf) {
+                return new Sdiv(machInst, rd, rn, rm);
+            }
+            break;
+          case 0x3:
+            if (op2 == 0 && m == 0 && ra == 0xf) {
+                return new Udiv(machInst, rd, rn, rm);
+            }
+            break;
           case 0x4:
             if (op2 == 0) {
                 if (m) {
-- 
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