From bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Apr 2009 21:44:15 -0700 Subject: Mem: Change isLlsc to isLLSC. --- src/cpu/checker/cpu.cc | 4 ++-- src/cpu/inorder/resources/cache_unit.cc | 6 +++--- src/cpu/o3/lsq_unit.hh | 4 ++-- src/cpu/o3/lsq_unit_impl.hh | 2 +- src/cpu/ozone/back_end_impl.hh | 2 +- src/cpu/ozone/inorder_back_end.hh | 2 +- src/cpu/ozone/lsq_unit_impl.hh | 6 +++--- src/cpu/ozone/lw_lsq.hh | 4 ++-- src/cpu/ozone/lw_lsq_impl.hh | 8 ++++---- src/cpu/simple/atomic.cc | 6 +++--- src/cpu/simple/timing.cc | 12 ++++++------ src/mem/cache/blk.hh | 4 ++-- src/mem/cache/cache_impl.hh | 4 ++-- src/mem/packet.hh | 4 ++-- src/mem/physical.cc | 10 +++++----- src/mem/physical.hh | 6 +++--- src/mem/request.hh | 2 +- 17 files changed, 43 insertions(+), 43 deletions(-) diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 4305f7ab0..fda0528ad 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -240,8 +240,8 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) // verify this data. if (unverifiedReq && !(unverifiedReq->isUncacheable()) && - (!(unverifiedReq->isLlsc()) || - ((unverifiedReq->isLlsc()) && + (!(unverifiedReq->isLLSC()) || + ((unverifiedReq->isLLSC()) && unverifiedReq->getExtraData() == 1))) { T inst_data; /* diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index ceaaf3532..772437638 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -355,7 +355,7 @@ CacheUnit::doDataAccess(DynInstPtr inst) Request *memReq = cache_req->dataPkt->req; - if (cache_req->dataPkt->isWrite() && memReq->isLlsc()) { + if (cache_req->dataPkt->isWrite() && memReq->isLLSC()) { assert(cache_req->inst->isStoreConditional()); DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n"); do_access = TheISA::handleLockedWrite(cpu, memReq); @@ -395,7 +395,7 @@ CacheUnit::doDataAccess(DynInstPtr inst) cacheStatus = cacheWaitResponse; cacheBlocked = false; } - } else if (!do_access && memReq->isLlsc()){ + } else if (!do_access && memReq->isLLSC()){ // Store-Conditional instructions complete even if they "failed" assert(cache_req->inst->isStoreConditional()); cache_req->setCompleted(true); @@ -471,7 +471,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) if (inst->isLoad()) { assert(cache_pkt->isRead()); - if (cache_pkt->req->isLlsc()) { + if (cache_pkt->req->isLLSC()) { DPRINTF(InOrderCachePort, "[tid:%u]: Handling Load-Linked for [sn:%u]\n", tid, inst->seqNum); diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 9f0f38f06..28e6f4506 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -514,7 +514,7 @@ LSQUnit::read(Request *req, T &data, int load_idx) "storeHead: %i addr: %#x\n", load_idx, store_idx, storeHead, req->getPaddr()); - if (req->isLlsc()) { + if (req->isLLSC()) { // Disable recording the result temporarily. Writing to misc // regs normally updates the result, but this is not the // desired behavior when handling store conditionals. @@ -647,7 +647,7 @@ LSQUnit::read(Request *req, T &data, int load_idx) if (!lsq->cacheBlocked()) { PacketPtr data_pkt = new Packet(req, - (req->isLlsc() ? + (req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq), Packet::Broadcast); data_pkt->dataStatic(load_inst->memData); diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index f5753a4ef..afc9faf9c 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -652,7 +652,7 @@ LSQUnit::writebackStores() MemCmd command = req->isSwap() ? MemCmd::SwapReq : - (req->isLlsc() ? MemCmd::StoreCondReq : MemCmd::WriteReq); + (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); data_pkt->dataStatic(inst->memData); diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh index ef3b0f182..7753a83b5 100644 --- a/src/cpu/ozone/back_end_impl.hh +++ b/src/cpu/ozone/back_end_impl.hh @@ -1256,7 +1256,7 @@ BackEnd::executeInsts() // ++iewExecStoreInsts; - if (!(inst->req->isLlsc())) { + if (!(inst->req->isLLSC())) { inst->setExecuted(); instToCommit(inst); diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index b30b37a22..96f3a901f 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -381,7 +381,7 @@ InorderBackEnd::write(MemReqPtr &req, T &data, int store_idx) } } /* - if (req->isLlsc()) { + if (req->isLLSC()) { if (req->isUncacheable()) { // Don't update result register (see stq_c in isa_desc) req->result = 2; diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh index 7e7bbdb01..833aa0581 100644 --- a/src/cpu/ozone/lsq_unit_impl.hh +++ b/src/cpu/ozone/lsq_unit_impl.hh @@ -577,7 +577,7 @@ OzoneLSQ::writebackStores() MemAccessResult result = dcacheInterface->access(req); //@todo temp fix for LL/SC (works fine for 1 CPU) - if (req->isLlsc()) { + if (req->isLLSC()) { req->result=1; panic("LL/SC! oh no no support!!!"); } @@ -596,7 +596,7 @@ OzoneLSQ::writebackStores() Event *wb = NULL; /* typename IEW::LdWritebackEvent *wb = NULL; - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port transaction. req->result=0; wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst, @@ -630,7 +630,7 @@ OzoneLSQ::writebackStores() // DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", // storeQueue[storeWBIdx].inst->seqNum); - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port transaction. req->result=1; typename BackEnd::LdWritebackEvent *wb = diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index 3ad8d1d64..6e9bb77af 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -635,7 +635,7 @@ OzoneLWLSQ::read(RequestPtr req, T &data, int load_idx) PacketPtr data_pkt = new Packet(req, - (req->isLlsc() ? + (req->isLLSC() ? MemCmd::LoadLockedReq : Packet::ReadReq), Packet::Broadcast); data_pkt->dataStatic(inst->memData); @@ -662,7 +662,7 @@ OzoneLWLSQ::read(RequestPtr req, T &data, int load_idx) return NoFault; } - if (req->isLlsc()) { + if (req->isLLSC()) { cpu->lockFlag = true; } diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 3943dab2d..4d290a1e9 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -589,7 +589,7 @@ OzoneLWLSQ::writebackStores() MemCmd command = req->isSwap() ? MemCmd::SwapReq : - (req->isLlsc() ? MemCmd::WriteReq : MemCmd::StoreCondReq); + (req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq); PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); data_pkt->dataStatic(inst->memData); @@ -606,7 +606,7 @@ OzoneLWLSQ::writebackStores() inst->seqNum); // @todo: Remove this SC hack once the memory system handles it. - if (req->isLlsc()) { + if (req->isLLSC()) { if (req->isUncacheable()) { req->setExtraData(2); } else { @@ -664,7 +664,7 @@ OzoneLWLSQ::writebackStores() if (result != MA_HIT && dcacheInterface->doEvents()) { store_event->miss = true; typename BackEnd::LdWritebackEvent *wb = NULL; - if (req->isLlsc()) { + if (req->isLLSC()) { wb = new typename BackEnd::LdWritebackEvent(inst, be); store_event->wbEvent = wb; @@ -691,7 +691,7 @@ OzoneLWLSQ::writebackStores() // DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", // inst->seqNum); - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port // transaction in the 21264, but that might be // hard to accomplish in this model. diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index eccdb2443..045b80c80 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -324,7 +324,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { Packet pkt = Packet(req, - req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, + req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, Packet::Broadcast); pkt.dataStatic(dataPtr); @@ -340,7 +340,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) assert(!pkt.isError()); - if (req->isLlsc()) { + if (req->isLLSC()) { TheISA::handleLockedRead(thread, req); } } @@ -468,7 +468,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access - if (req->isLlsc()) { + if (req->isLLSC()) { cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req); } else if (req->isSwap()) { diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 905acb6d4..590ba6b2d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -290,7 +290,7 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req, } else { bool do_access = true; // flag to suppress cache access - if (req->isLlsc()) { + if (req->isLLSC()) { do_access = TheISA::handleLockedWrite(thread, req); } else if (req->isCondSwap()) { assert(res); @@ -384,11 +384,11 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) MemCmd cmd; if (read) { cmd = MemCmd::ReadReq; - if (req->isLlsc()) + if (req->isLLSC()) cmd = MemCmd::LoadLockedReq; } else { cmd = MemCmd::WriteReq; - if (req->isLlsc()) { + if (req->isLLSC()) { cmd = MemCmd::StoreCondReq; } else if (req->isSwap()) { cmd = MemCmd::SwapReq; @@ -452,7 +452,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) _status = DTBWaitResponse; if (split_addr > addr) { RequestPtr req1, req2; - assert(!req->isLlsc() && !req->isSwap()); + assert(!req->isLLSC() && !req->isSwap()); req->splitOnVaddr(split_addr, req1, req2); typedef SplitDataTranslation::WholeTranslationState WholeState; @@ -571,7 +571,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) _status = DTBWaitResponse; if (split_addr > addr) { RequestPtr req1, req2; - assert(!req->isLlsc() && !req->isSwap()); + assert(!req->isLLSC() && !req->isSwap()); req->splitOnVaddr(split_addr, req1, req2); typedef SplitDataTranslation::WholeTranslationState WholeState; @@ -904,7 +904,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) // the locked flag may be cleared on the response packet, so check // pkt->req and not pkt to see if it was a load-locked - if (pkt->isRead() && pkt->req->isLlsc()) { + if (pkt->isRead() && pkt->req->isLLSC()) { TheISA::handleLockedRead(thread, pkt->req); } diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh index acb117f6c..ab15355bd 100644 --- a/src/mem/cache/blk.hh +++ b/src/mem/cache/blk.hh @@ -218,7 +218,7 @@ class CacheBlk */ void trackLoadLocked(PacketPtr pkt) { - assert(pkt->isLlsc()); + assert(pkt->isLLSC()); lockList.push_front(Lock(pkt->req)); } @@ -236,7 +236,7 @@ class CacheBlk bool checkWrite(PacketPtr pkt) { Request *req = pkt->req; - if (pkt->isLlsc()) { + if (pkt->isLLSC()) { // it's a store conditional... have to check for matching // load locked. bool success = false; diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index f98d6ac34..ea8ae0046 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -180,7 +180,7 @@ Cache::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk) pkt->writeDataToBlock(blk->data, blkSize); } } else if (pkt->isRead()) { - if (pkt->isLlsc()) { + if (pkt->isLLSC()) { blk->trackLoadLocked(pkt); } pkt->setDataFromBlock(blk->data, blkSize); @@ -317,7 +317,7 @@ Cache::access(PacketPtr pkt, BlkType *&blk, incMissCount(pkt); - if (blk == NULL && pkt->isLlsc() && pkt->isWrite()) { + if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { // complete miss on store conditional... just give up now pkt->req->setExtraData(0); return true; diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 965482c02..b06f53336 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -166,7 +166,7 @@ class MemCmd bool isInvalidate() const { return testCmdAttrib(IsInvalidate); } bool hasData() const { return testCmdAttrib(HasData); } bool isReadWrite() const { return isRead() && isWrite(); } - bool isLlsc() const { return testCmdAttrib(IsLlsc); } + bool isLLSC() const { return testCmdAttrib(IsLlsc); } bool isError() const { return testCmdAttrib(IsError); } bool isPrint() const { return testCmdAttrib(IsPrint); } @@ -401,7 +401,7 @@ class Packet : public FastAlloc, public Printable bool isInvalidate() const { return cmd.isInvalidate(); } bool hasData() const { return cmd.hasData(); } bool isReadWrite() const { return cmd.isReadWrite(); } - bool isLlsc() const { return cmd.isLlsc(); } + bool isLLSC() const { return cmd.isLLSC(); } bool isError() const { return cmd.isError(); } bool isPrint() const { return cmd.isPrint(); } diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 86ecb506f..4a521717e 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -162,12 +162,12 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt) { Request *req = pkt->req; Addr paddr = LockedAddr::mask(req->getPaddr()); - bool isLlsc = pkt->isLlsc(); + bool isLLSC = pkt->isLLSC(); // Initialize return value. Non-conditional stores always // succeed. Assume conditional stores will fail until proven // otherwise. - bool success = !isLlsc; + bool success = !isLLSC; // Iterate over list. Note that there could be multiple matching // records, as more than one context could have done a load locked @@ -179,7 +179,7 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt) if (i->addr == paddr) { // we have a matching address - if (isLlsc && i->matchesContext(req)) { + if (isLLSC && i->matchesContext(req)) { // it's a store conditional, and as far as the memory // system can tell, the requesting context's lock is // still valid. @@ -199,7 +199,7 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt) } } - if (isLlsc) { + if (isLLSC) { req->setExtraData(success ? 1 : 0); } @@ -284,7 +284,7 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt) TRACE_PACKET("Read/Write"); } else if (pkt->isRead()) { assert(!pkt->isWrite()); - if (pkt->isLlsc()) { + if (pkt->isLLSC()) { trackLoadLocked(pkt); } if (pmemAddr) diff --git a/src/mem/physical.hh b/src/mem/physical.hh index 2a3bea7a5..8dbadccc4 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -129,11 +129,11 @@ class PhysicalMemory : public MemObject Request *req = pkt->req; if (lockedAddrList.empty()) { // no locked addrs: nothing to check, store_conditional fails - bool isLlsc = pkt->isLlsc(); - if (isLlsc) { + bool isLLSC = pkt->isLLSC(); + if (isLLSC) { req->setExtraData(0); } - return !isLlsc; // only do write if not an sc + return !isLLSC; // only do write if not an sc } else { // iterate over list... return checkLockedAddrList(pkt); diff --git a/src/mem/request.hh b/src/mem/request.hh index 6e56c07b3..64f6ad053 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -450,7 +450,7 @@ class Request : public FastAlloc /** Accessor Function to Check Cacheability. */ bool isUncacheable() const { return flags.isSet(UNCACHEABLE); } bool isInstRead() const { return flags.isSet(INST_READ); } - bool isLlsc() const { return flags.isSet(LLSC); } + bool isLLSC() const { return flags.isSet(LLSC); } bool isLocked() const { return flags.isSet(LOCKED); } bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); } bool isCondSwap() const { return flags.isSet(MEM_SWAP_COND); } -- cgit v1.2.3