From 2a67f2b08cb2d478c3b425d778a75bb2ce46a813 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 21 Feb 2007 14:08:13 -0800 Subject: Fix tracing so it starts right away if --trace-start is not specified. --HG-- extra : convert_revision : 49c1ea0b8c313949124aed84b1055db0b3c55bd8 --- src/python/m5/main.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 48c75434f..37df884d0 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -297,7 +297,7 @@ def main(): internal.trace.cvar.enabled = True internal.event.create(enable_trace, int(options.trace_start)) else: - internal.trace.enabled = True + internal.trace.cvar.enabled = True internal.trace.output(options.trace_file) -- cgit v1.2.3 From 06ae2d04455d39acb1db642952e56b6a0359cf22 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 21 Feb 2007 16:42:16 -0800 Subject: Fix compile issues on gcc 4.1.x related to namespaces. This basically involves moving the builder code outside of any namespace. While we're at it, move a few braces outside of a couple #if/#else/#endif blocks so it's easier to match up the braces. --HG-- extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312 --- src/arch/alpha/tlb.cc | 21 ++++++++++++--------- src/arch/sparc/tlb.cc | 7 ++++--- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index c21bf94f5..1e0155138 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -46,8 +46,7 @@ using namespace std; using namespace EV5; -namespace AlphaISA -{ +namespace AlphaISA { /////////////////////////////////////////////////////////////////////// // // Alpha TLB @@ -116,10 +115,11 @@ TLB::checkCacheability(RequestPtr &req) #if ALPHA_TLASER - if (req->getPaddr() & PAddrUncachedBit39) { + if (req->getPaddr() & PAddrUncachedBit39) #else - if (req->getPaddr() & PAddrUncachedBit43) { + if (req->getPaddr() & PAddrUncachedBit43) #endif + { // IPR memory space not implemented if (PAddrIprSpace(req->getPaddr())) { return new UnimpFault("IPR memory space not implemented!"); @@ -313,10 +313,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) { + VAddrSpaceEV5(req->getVaddr()) == 2) #else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) #endif + { // only valid in kernel mode if (ICM_CM(tc->readMiscReg(IPR_ICM)) != mode_kernel) { @@ -487,10 +488,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const // Check for "superpage" mapping #if ALPHA_TLASER if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) { + VAddrSpaceEV5(req->getVaddr()) == 2) #else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) #endif + { // only valid in kernel mode if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != @@ -592,6 +594,8 @@ TLB::index(bool advance) return *pte; } +/* end namespace AlphaISA */ } + DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) @@ -633,4 +637,3 @@ CREATE_SIM_OBJECT(DTB) } REGISTER_SIM_OBJECT("AlphaDTB", DTB) -} diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 82b1ed175..8a9ea3d0e 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -43,8 +43,7 @@ /* @todo remove some of the magic constants. -- ali * */ -namespace SparcISA -{ +namespace SparcISA { TLB::TLB(const std::string &name, int s) : SimObject(name), size(s), usedEntries(0), lastReplaced(0), @@ -1329,6 +1328,9 @@ TLB::unserialize(Checkpoint *cp, const std::string §ion) } } +/* end namespace SparcISA */ } + +using namespace SparcISA; DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) @@ -1371,4 +1373,3 @@ CREATE_SIM_OBJECT(DTB) } REGISTER_SIM_OBJECT("SparcDTB", DTB) -} -- cgit v1.2.3 From 7a2ecf9e268bf10fc0a2406f3a928a661e97b5fd Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 21 Feb 2007 21:06:17 -0500 Subject: add pseduo instruction support for sparc util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha --HG-- rename : util/m5/Makefile => util/m5/Makefile.sparc rename : util/m5/m5op.S => util/m5/m5op_alpha.S extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834 --- src/arch/alpha/isa/decoder.isa | 36 +++---- src/arch/sparc/isa/bitfields.isa | 1 + src/arch/sparc/isa/decoder.isa | 14 ++- src/arch/sparc/isa/includes.isa | 4 + src/arch/sparc/isa/operands.isa | 6 ++ src/arch/sparc/tlb.cc | 47 ++++++--- src/sim/pseudo_inst.cc | 2 +- src/sim/pseudo_inst.hh | 2 +- util/m5/Makefile | 53 ---------- util/m5/Makefile.alpha | 53 ++++++++++ util/m5/Makefile.sparc | 53 ++++++++++ util/m5/m5.c | 19 +--- util/m5/m5op.S | 210 --------------------------------------- util/m5/m5op.h | 2 +- util/m5/m5op_alpha.S | 189 +++++++++++++++++++++++++++++++++++ util/m5/m5op_sparc.S | 152 ++++++++++++++++++++++++++++ util/m5/m5ops.h | 54 ++++++++++ 17 files changed, 577 insertions(+), 320 deletions(-) delete mode 100644 util/m5/Makefile create mode 100644 util/m5/Makefile.alpha create mode 100644 util/m5/Makefile.sparc delete mode 100644 util/m5/m5op.S create mode 100644 util/m5/m5op_alpha.S create mode 100644 util/m5/m5op_sparc.S create mode 100644 util/m5/m5ops.h diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 1da6a60f1..49c25c3c2 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -790,19 +790,19 @@ decode OPCODE default Unknown::unknown() { // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { 0x00: arm({{ - AlphaPseudo::arm(xc->tcBase()); + PseudoInst::arm(xc->tcBase()); }}, IsNonSpeculative); 0x01: quiesce({{ - AlphaPseudo::quiesce(xc->tcBase()); + PseudoInst::quiesce(xc->tcBase()); }}, IsNonSpeculative, IsQuiesce); 0x02: quiesceNs({{ - AlphaPseudo::quiesceNs(xc->tcBase(), R16); + PseudoInst::quiesceNs(xc->tcBase(), R16); }}, IsNonSpeculative, IsQuiesce); 0x03: quiesceCycles({{ - AlphaPseudo::quiesceCycles(xc->tcBase(), R16); + PseudoInst::quiesceCycles(xc->tcBase(), R16); }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 0x04: quiesceTime({{ - R0 = AlphaPseudo::quiesceTime(xc->tcBase()); + R0 = PseudoInst::quiesceTime(xc->tcBase()); }}, IsNonSpeculative, IsUnverifiable); 0x10: ivlb({{ warn_once("Obsolete M5 instruction ivlb encountered.\n"); @@ -811,47 +811,47 @@ decode OPCODE default Unknown::unknown() { warn_once("Obsolete M5 instruction ivlb encountered.\n"); }}); 0x20: m5exit_old({{ - AlphaPseudo::m5exit_old(xc->tcBase()); + PseudoInst::m5exit_old(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x21: m5exit({{ - AlphaPseudo::m5exit(xc->tcBase(), R16); + PseudoInst::m5exit(xc->tcBase(), R16); }}, No_OpClass, IsNonSpeculative); 0x31: loadsymbol({{ - AlphaPseudo::loadsymbol(xc->tcBase()); + PseudoInst::loadsymbol(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }}); 0x40: resetstats({{ - AlphaPseudo::resetstats(xc->tcBase(), R16, R17); + PseudoInst::resetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x41: dumpstats({{ - AlphaPseudo::dumpstats(xc->tcBase(), R16, R17); + PseudoInst::dumpstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x42: dumpresetstats({{ - AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17); + PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x43: m5checkpoint({{ - AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17); + PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x50: m5readfile({{ - R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18); + R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); }}, IsNonSpeculative); 0x51: m5break({{ - AlphaPseudo::debugbreak(xc->tcBase()); + PseudoInst::debugbreak(xc->tcBase()); }}, IsNonSpeculative); 0x52: m5switchcpu({{ - AlphaPseudo::switchcpu(xc->tcBase()); + PseudoInst::switchcpu(xc->tcBase()); }}, IsNonSpeculative); 0x53: m5addsymbol({{ - AlphaPseudo::addsymbol(xc->tcBase(), R16, R17); + PseudoInst::addsymbol(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x54: m5panic({{ panic("M5 panic instruction called at pc=%#x.", xc->readPC()); }}, IsNonSpeculative); 0x55: m5anBegin({{ - AlphaPseudo::anBegin(xc->tcBase(), R16); + PseudoInst::anBegin(xc->tcBase(), R16); }}, IsNonSpeculative); 0x56: m5anWait({{ - AlphaPseudo::anWait(xc->tcBase(), R16, R17); + PseudoInst::anWait(xc->tcBase(), R16, R17); }}, IsNonSpeculative); } } diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa index e75680d2b..afa8f88a2 100644 --- a/src/arch/sparc/isa/bitfields.isa +++ b/src/arch/sparc/isa/bitfields.isa @@ -54,6 +54,7 @@ def bitfield FCN <29:25>; def bitfield I <13>; def bitfield IMM_ASI <12:5>; def bitfield IMM22 <21:0>; +def bitfield M5FUNC <15:7>; def bitfield MMASK <3:0>; def bitfield OP <31:30>; def bitfield OP2 <24:22>; diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 0be7defba..e2d1707dd 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1009,7 +1009,16 @@ decode OP default Unknown::unknown() 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 0x81: FailUnimpl::siam(); } - 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); + // M5 special opcodes use the reserved IMPDEP2A opcode space + 0x37: decode M5FUNC { + // we have 7 bits of space here to play with... + 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); + }}, No_OpClass, IsNonSpeculative); + 0x54: m5panic({{ + panic("M5 panic instruction called at pc=%#x.", xc->readPC()); + }}, No_OpClass, IsNonSpeculative); + + } 0x38: Branch::jmpl({{ Addr target = Rs1 + Rs2_or_imm13; if(target & 0x3) @@ -1077,7 +1086,8 @@ decode OP default Unknown::unknown() } }}, IsSerializeAfter, IsNonSpeculative); } - 0x3B: Nop::flush({{/*Instruction memory flush*/}}); + 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, + MemWriteOp); 0x3C: save({{ if(Cansave == 0) { diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index b46ef011e..05e9e8731 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -70,6 +70,10 @@ output exec {{ #include #endif +#if FULL_SYSTEM +#include "sim/pseudo_inst.hh" +#endif + #include #include diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index f624c3e2b..82e9407de 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -100,6 +100,12 @@ def operands {{ 'R1': ('IntReg', 'udw', '1', None, 7), 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 'R16': ('IntReg', 'udw', '16', None, 9), + 'O0': ('IntReg', 'udw', '24', 'IsInteger', 10), + 'O1': ('IntReg', 'udw', '25', 'IsInteger', 11), + 'O2': ('IntReg', 'udw', '26', 'IsInteger', 12), + 'O3': ('IntReg', 'udw', '27', 'IsInteger', 13), + 'O4': ('IntReg', 'udw', '28', 'IsInteger', 14), + 'O5': ('IntReg', 'udw', '29', 'IsInteger', 15), # Control registers # 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 82b1ed175..3ed2a9cc6 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -596,21 +596,36 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) // Be fast if we can! if (cacheValid && cacheState == tlbdata) { - if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && - cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr && - (!write || cacheEntry[0]->pte.writable())) { - req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | - vaddr & cacheEntry[0]->pte.size()-1 ); - return NoFault; - } - if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && - cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr && - (!write || cacheEntry[1]->pte.writable())) { - req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | - vaddr & cacheEntry[1]->pte.size()-1 ); - return NoFault; - } - } + + + + if (cacheEntry[0]) { + TlbEntry *ce = cacheEntry[0]; + Addr ce_va = ce->range.va; + if (cacheAsi[0] == asi && + ce_va < vaddr + size && ce_va + ce->range.size > vaddr && + (!write || ce->pte.writable())) { + req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); + if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) + req->setFlags(req->getFlags() | UNCACHEABLE); + DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); + return NoFault; + } // if matched + } // if cache entry valid + if (cacheEntry[1]) { + TlbEntry *ce = cacheEntry[1]; + Addr ce_va = ce->range.va; + if (cacheAsi[1] == asi && + ce_va < vaddr + size && ce_va + ce->range.size > vaddr && + (!write || ce->pte.writable())) { + req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); + if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) + req->setFlags(req->getFlags() | UNCACHEABLE); + DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); + return NoFault; + } // if matched + } // if cache entry valid + } bool red = bits(tlbdata,1,1); bool priv = bits(tlbdata,2,2); @@ -756,7 +771,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) } - if (e->pte.sideffect()) + if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) req->setFlags(req->getFlags() | UNCACHEABLE); // cache translation date for next translation diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 66ebc10e1..56a779674 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -55,7 +55,7 @@ using namespace std; using namespace Stats; using namespace TheISA; -namespace AlphaPseudo +namespace PseudoInst { void arm(ThreadContext *tc) diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index bc71a7e64..93021abad 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -33,7 +33,7 @@ class ThreadContext; //We need the "Tick" and "Addr" data types from here #include "sim/host.hh" -namespace AlphaPseudo +namespace PseudoInst { /** * @todo these externs are only here for a hack in fullCPU::takeOver... diff --git a/util/m5/Makefile b/util/m5/Makefile deleted file mode 100644 index a98092e47..000000000 --- a/util/m5/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright (c) 2005-2006 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert -# Ali Saidi - -### If we are not compiling on an alpha, we must use cross tools ### -ifneq ($(shell uname -m), alpha) -CROSS_COMPILE?=alpha-unknown-linux-gnu- -endif -CC=$(CROSS_COMPILE)gcc -AS=$(CROSS_COMPILE)as -LD=$(CROSS_COMPILE)ld - -CFLAGS=-O2 -OBJS=m5.o m5op.o - -all: m5 - -%.o: %.S - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -m5: $(OBJS) - $(CC) -o $@ $(OBJS) - -clean: - rm -f *.o m5 diff --git a/util/m5/Makefile.alpha b/util/m5/Makefile.alpha new file mode 100644 index 000000000..e94c2901d --- /dev/null +++ b/util/m5/Makefile.alpha @@ -0,0 +1,53 @@ +# Copyright (c) 2005-2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert +# Ali Saidi + +### If we are not compiling on an alpha, we must use cross tools ### +ifneq ($(shell uname -m), alpha) +CROSS_COMPILE?=alpha-unknown-linux-gnu- +endif +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)ld + +CFLAGS=-O2 +OBJS=m5.o m5op_alpha.o + +all: m5 + +%.o: %.S + $(CC) $(CFLAGS) -o $@ -c $< + +%.o: %.c + $(CC) $(CFLAGS) -o $@ -c $< + +m5: $(OBJS) + $(CC) -o $@ $(OBJS) + +clean: + rm -f *.o m5 diff --git a/util/m5/Makefile.sparc b/util/m5/Makefile.sparc new file mode 100644 index 000000000..835ccb2a4 --- /dev/null +++ b/util/m5/Makefile.sparc @@ -0,0 +1,53 @@ +# Copyright (c) 2005-2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert +# Ali Saidi + +### If we are not compiling on an alpha, we must use cross tools ### +ifneq ($(shell uname -m), sun4v) +CROSS_COMPILE?=sparc64-sun-solaris2.10- +endif +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)ld + +CFLAGS=-O2 +OBJS=m5.o m5op_sparc.o + +all: m5 + +%.o: %.S + $(CC) $(CFLAGS) -o $@ -c $< + +%.o: %.c + $(CC) $(CFLAGS) -o $@ -c $< + +m5: $(OBJS) + $(CC) -o $@ $(OBJS) + +clean: + rm -f *.o m5 diff --git a/util/m5/m5.c b/util/m5/m5.c index ca555ed12..190289f06 100644 --- a/util/m5/m5.c +++ b/util/m5/m5.c @@ -70,24 +70,6 @@ main(int argc, char *argv[]) command = argv[1]; - if (COMPARE("ivlb")) { - if (argc != 3) - usage(); - - arg1 = strtoul(argv[2], NULL, 0); - m5_ivlb(arg1); - return 0; - } - - if (COMPARE("ivle")) { - if (argc != 3) - usage(); - - arg1 = strtoul(argv[2], NULL, 0); - m5_ivle(arg1); - return 0; - } - if (COMPARE("initparam")) { if (argc != 2) usage(); @@ -203,6 +185,7 @@ main(int argc, char *argv[]) if (COMPARE("loadsymbol")) { m5_loadsymbol(arg1); return 0; + } if (COMPARE("readfile")) { char buf[256*1024]; int offset = 0; diff --git a/util/m5/m5op.S b/util/m5/m5op.S deleted file mode 100644 index 61e79d5d3..000000000 --- a/util/m5/m5op.S +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2003-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - */ - -#define m5_op 0x01 - -#define arm_func 0x00 -#define quiesce_func 0x01 -#define quiescens_func 0x02 -#define quiescecycle_func 0x03 -#define quiescetime_func 0x04 -#define ivlb 0x10 // obsolete -#define ivle 0x11 // obsolete -#define exit_old_func 0x20 // deprecated! -#define exit_func 0x21 -#define initparam_func 0x30 -#define loadsymbol_func 0x31 -#define resetstats_func 0x40 -#define dumpstats_func 0x41 -#define dumprststats_func 0x42 -#define ckpt_func 0x43 -#define readfile_func 0x50 -#define debugbreak_func 0x51 -#define switchcpu_func 0x52 -#define addsymbol_func 0x53 -#define panic_func 0x54 -#define anbegin_func 0x55 -#define anwait_func 0x56 - -#define INST(op, ra, rb, func) \ - .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) - -#define LEAF(func) \ - .align 3; \ - .globl func; \ - .ent func; \ -func: - -#define RET \ - ret ($26) - -#define END(func) \ - .end func - -#define ARM(reg) INST(m5_op, reg, 0, arm_func) -#define QUIESCE INST(m5_op, 0, 0, quiesce_func) -#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) -#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) -#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) -#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) -#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) -#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func) -#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) -#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) -#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) -#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) -#define READFILE INST(m5_op, 0, 0, readfile_func) -#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) -#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) -#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) -#define PANIC INST(m5_op, 0, 0, panic_func) -#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func) -#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func) - - .set noreorder - - .align 4 -LEAF(arm) - ARM(16) - RET -END(arm) - - .align 4 -LEAF(quiesce) - QUIESCE - RET -END(quiesce) - - .align 4 -LEAF(quiesceNs) - QUIESCENS(16) - RET -END(quiesceNs) - - .align 4 -LEAF(quiesceCycle) - QUIESCECYC(16) - RET -END(quiesceCycle) - - .align 4 -LEAF(quiesceTime) - QUIESCETIME - RET -END(quiesceTime) - - .align 4 -LEAF(m5_exit) - M5EXIT(16) - RET -END(m5_exit) - - .align 4 -LEAF(m5_initparam) - INITPARAM(0) - RET -END(m5_initparam) - - .align 4 -LEAF(m5_loadsymbol) - LOADSYMBOL(0) - RET -END(m5_loadsymbol) - - .align 4 -LEAF(m5_reset_stats) - RESET_STATS(16, 17) - RET -END(m5_reset_stats) - - .align 4 -LEAF(m5_dump_stats) - DUMP_STATS(16, 17) - RET -END(m5_dump_stats) - - .align 4 -LEAF(m5_dumpreset_stats) - DUMPRST_STATS(16, 17) - RET -END(m5_dumpreset_stats) - - .align 4 -LEAF(m5_checkpoint) - CHECKPOINT(16, 17) - RET -END(m5_checkpoint) - - .align 4 -LEAF(m5_readfile) - READFILE - RET -END(m5_readfile) - - .align 4 -LEAF(m5_debugbreak) - DEBUGBREAK - RET -END(m5_debugbreak) - - .align 4 -LEAF(m5_switchcpu) - SWITCHCPU - RET -END(m5_switchcpu) - - .align 4 -LEAF(m5_addsymbol) - ADDSYMBOL(16, 17) - RET -END(m5_addsymbol) - - .align 4 -LEAF(m5_panic) - PANIC - RET -END(m5_panic) - - - .align 4 -LEAF(m5_anbegin) - AN_BEGIN(16) - RET -END(m5_anbegin) - - - .align 4 -LEAF(m5_anwait) - AN_WAIT(16,17) - RET -END(m5_anwait) - - diff --git a/util/m5/m5op.h b/util/m5/m5op.h index e8f2baaac..f4e6bb0f1 100644 --- a/util/m5/m5op.h +++ b/util/m5/m5op.h @@ -32,7 +32,7 @@ #ifndef __M5OP_H__ #define __M5OP_H__ -#include +#include void arm(uint64_t address); void quiesce(void); diff --git a/util/m5/m5op_alpha.S b/util/m5/m5op_alpha.S new file mode 100644 index 000000000..c5d0e65f8 --- /dev/null +++ b/util/m5/m5op_alpha.S @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Ali Saidi + */ + +#define m5_op 0x01 + +#include "m5ops.h" + +#define INST(op, ra, rb, func) \ + .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) + +#define LEAF(func) \ + .align 3; \ + .globl func; \ + .ent func; \ +func: + +#define RET \ + ret ($26) + +#define END(func) \ + .end func + +#define ARM(reg) INST(m5_op, reg, 0, arm_func) +#define QUIESCE INST(m5_op, 0, 0, quiesce_func) +#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) +#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) +#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) +#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) +#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) +#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func) +#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) +#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) +#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) +#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) +#define READFILE INST(m5_op, 0, 0, readfile_func) +#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) +#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) +#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) +#define PANIC INST(m5_op, 0, 0, panic_func) +#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func) +#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func) + + .set noreorder + + .align 4 +LEAF(arm) + ARM(16) + RET +END(arm) + + .align 4 +LEAF(quiesce) + QUIESCE + RET +END(quiesce) + + .align 4 +LEAF(quiesceNs) + QUIESCENS(16) + RET +END(quiesceNs) + + .align 4 +LEAF(quiesceCycle) + QUIESCECYC(16) + RET +END(quiesceCycle) + + .align 4 +LEAF(quiesceTime) + QUIESCETIME + RET +END(quiesceTime) + + .align 4 +LEAF(m5_exit) + M5EXIT(16) + RET +END(m5_exit) + + .align 4 +LEAF(m5_initparam) + INITPARAM(0) + RET +END(m5_initparam) + + .align 4 +LEAF(m5_loadsymbol) + LOADSYMBOL(0) + RET +END(m5_loadsymbol) + + .align 4 +LEAF(m5_reset_stats) + RESET_STATS(16, 17) + RET +END(m5_reset_stats) + + .align 4 +LEAF(m5_dump_stats) + DUMP_STATS(16, 17) + RET +END(m5_dump_stats) + + .align 4 +LEAF(m5_dumpreset_stats) + DUMPRST_STATS(16, 17) + RET +END(m5_dumpreset_stats) + + .align 4 +LEAF(m5_checkpoint) + CHECKPOINT(16, 17) + RET +END(m5_checkpoint) + + .align 4 +LEAF(m5_readfile) + READFILE + RET +END(m5_readfile) + + .align 4 +LEAF(m5_debugbreak) + DEBUGBREAK + RET +END(m5_debugbreak) + + .align 4 +LEAF(m5_switchcpu) + SWITCHCPU + RET +END(m5_switchcpu) + + .align 4 +LEAF(m5_addsymbol) + ADDSYMBOL(16, 17) + RET +END(m5_addsymbol) + + .align 4 +LEAF(m5_panic) + PANIC + RET +END(m5_panic) + + + .align 4 +LEAF(m5_anbegin) + AN_BEGIN(16) + RET +END(m5_anbegin) + + + .align 4 +LEAF(m5_anwait) + AN_WAIT(16,17) + RET +END(m5_anwait) + + diff --git a/util/m5/m5op_sparc.S b/util/m5/m5op_sparc.S new file mode 100644 index 000000000..b5c421bdf --- /dev/null +++ b/util/m5/m5op_sparc.S @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Ali Saidi + */ + +#define m5_op 0x2 +#define m5_op3 0x37 + +#include "m5ops.h" + +#define INST(func, rs1, rs2, rd) \ + .long (m5_op) << 30 | (rd) << 25 | (m5_op3) << 19 | (func) << 7 | \ + (rs1) << 14 | (rs2) << 0; + + +#define LEAF(func) \ + .section ".text"; \ + .align 4; \ + .global func; \ + .type func, #function; \ +func: + +#define END(func) \ + .size func, (.-func) + +#define M5EXIT INST(exit_func, 0, 0, 0) +#define PANIC INST(panic_func, 0, 0, 0) + +LEAF(m5_exit) + retl + M5EXIT +END(m5_exit) + +LEAF(m5_panic) + retl + PANIC +END(m5_panic) + + +/* !!!!!! All code below here just panics !!!!!! */ +LEAF(arm) + retl + PANIC +END(arm) + +LEAF(quiesce) + retl + PANIC +END(quiesce) + +LEAF(quiesceNs) + retl + PANIC +END(quiesceNs) + +LEAF(quiesceCycle) + retl + PANIC +END(quiesceCycle) + +LEAF(quiesceTime) + retl + PANIC +END(quiesceTime) + +LEAF(m5_initparam) + retl + PANIC +END(m5_initparam) + +LEAF(m5_loadsymbol) + retl + PANIC +END(m5_loadsymbol) + +LEAF(m5_reset_stats) + retl + PANIC +END(m5_reset_stats) + +LEAF(m5_dump_stats) + retl + PANIC +END(m5_dump_stats) + +LEAF(m5_dumpreset_stats) + retl + PANIC +END(m5_dumpreset_stats) + +LEAF(m5_checkpoint) + retl + PANIC +END(m5_checkpoint) + +LEAF(m5_readfile) + retl + PANIC +END(m5_readfile) + +LEAF(m5_debugbreak) + retl + PANIC +END(m5_debugbreak) + +LEAF(m5_switchcpu) + retl + PANIC +END(m5_switchcpu) + +LEAF(m5_addsymbol) + retl + PANIC +END(m5_addsymbol) + +LEAF(m5_anbegin) + retl + PANIC +END(m5_anbegin) + +LEAF(m5_anwait) + retl + PANIC +END(m5_anwait) + + diff --git a/util/m5/m5ops.h b/util/m5/m5ops.h new file mode 100644 index 000000000..ce0b39b29 --- /dev/null +++ b/util/m5/m5ops.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Ali Saidi + */ + +#define arm_func 0x00 +#define quiesce_func 0x01 +#define quiescens_func 0x02 +#define quiescecycle_func 0x03 +#define quiescetime_func 0x04 +#define ivlb 0x10 // obsolete +#define ivle 0x11 // obsolete +#define exit_old_func 0x20 // deprecated! +#define exit_func 0x21 +#define initparam_func 0x30 +#define loadsymbol_func 0x31 +#define resetstats_func 0x40 +#define dumpstats_func 0x41 +#define dumprststats_func 0x42 +#define ckpt_func 0x43 +#define readfile_func 0x50 +#define debugbreak_func 0x51 +#define switchcpu_func 0x52 +#define addsymbol_func 0x53 +#define panic_func 0x54 +#define anbegin_func 0x55 +#define anwait_func 0x56 + -- cgit v1.2.3 From 8e77d771f97cdff339b1a9e98b1e2caea7280f29 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 21 Feb 2007 20:35:30 -0800 Subject: Make comments refer to ticks not cycles --HG-- extra : convert_revision : 4970a76890a3256073423a827dd0c55cfcb19a08 --- src/base/statistics.hh | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 8168473a1..761b30c2b 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -70,7 +70,7 @@ class Callback; -/** The current simulated cycle. */ +/** The current simulated tick. */ extern Tick curTick; /* A namespace for all of the Statistics */ @@ -598,9 +598,9 @@ struct StatStor }; /** - * Templatized storage and interface to a per-cycle average stat. This keeps - * a current count and updates a total (count * cycles) when this count - * changes. This allows the quick calculation of a per cycle count of the item + * Templatized storage and interface to a per-tick average stat. This keeps + * a current count and updates a total (count * ticks) when this count + * changes. This allows the quick calculation of a per tick count of the item * being watched. This is good for keeping track of residencies in structures * among other things. */ @@ -613,9 +613,9 @@ struct AvgStor private: /** The current count. */ Counter current; - /** The total count for all cycles. */ + /** The total count for all tick. */ mutable Result total; - /** The cycle that current last changed. */ + /** The tick that current last changed. */ mutable Tick last; public: @@ -1563,7 +1563,7 @@ struct FancyStor }; /** - * Templatized storage for distribution that calculates per cycle mean and + * Templatized storage for distribution that calculates per tick mean and * variance. */ struct AvgFancy @@ -2280,7 +2280,7 @@ class Value : public Wrap }; /** - * A stat that calculates the per cycle average of a value. + * A stat that calculates the per tick average of a value. * @sa Stat, ScalarBase, AvgStor */ template @@ -2417,7 +2417,7 @@ class StandardDeviation }; /** - * Calculates the per cycle mean and variance of the samples. + * Calculates the per tick mean and variance of the samples. * @sa Stat, DistBase, AvgFancy */ template -- cgit v1.2.3 From 783e642ed8cf45e65ddb7a47f5bd2c34df1900cd Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 21 Feb 2007 20:45:05 -0800 Subject: Make sure that all variables in the NSGigE device model are initialized. --HG-- extra : convert_revision : b4b156ed8e3c0c4c4f8043ff86dc232ebad38668 --- src/dev/ns_gige.cc | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 74f9d88d1..86f56b62e 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -92,28 +92,30 @@ NSGigE::NSGigE(Params *p) : PciDev(p), ioEnable(false), txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size), txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL), - txXferLen(0), rxXferLen(0), clock(p->clock), - txState(txIdle), txEnable(false), CTDD(false), + txXferLen(0), rxXferLen(0), rxDmaFree(false), txDmaFree(false), + clock(p->clock), + txState(txIdle), txEnable(false), CTDD(false), txHalt(false), txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle), - rxEnable(false), CRDD(false), rxPktBytes(0), + rxEnable(false), CRDD(false), rxPktBytes(0), rxHalt(false), rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false), - eepromState(eepromStart), rxDmaReadEvent(this), rxDmaWriteEvent(this), + eepromState(eepromStart), eepromClk(false), eepromBitsToRx(0), + eepromOpcode(0), eepromAddress(0), eepromData(0), + dmaReadDelay(p->dma_read_delay), dmaWriteDelay(p->dma_write_delay), + dmaReadFactor(p->dma_read_factor), dmaWriteFactor(p->dma_write_factor), + rxDmaData(NULL), rxDmaAddr(0), rxDmaLen(0), + txDmaData(NULL), txDmaAddr(0), txDmaLen(0), + rxDmaReadEvent(this), rxDmaWriteEvent(this), txDmaReadEvent(this), txDmaWriteEvent(this), dmaDescFree(p->dma_desc_free), dmaDataFree(p->dma_data_free), txDelay(p->tx_delay), rxDelay(p->rx_delay), rxKickTick(0), rxKickEvent(this), txKickTick(0), txKickEvent(this), - txEvent(this), rxFilterEnable(p->rx_filter), acceptBroadcast(false), - acceptMulticast(false), acceptUnicast(false), + txEvent(this), rxFilterEnable(p->rx_filter), + acceptBroadcast(false), acceptMulticast(false), acceptUnicast(false), acceptPerfect(false), acceptArp(false), multicastHashEnable(false), - intrTick(0), cpuPendingIntr(false), + intrDelay(p->intr_delay), intrTick(0), cpuPendingIntr(false), intrEvent(0), interface(0) { - intrDelay = p->intr_delay; - dmaReadDelay = p->dma_read_delay; - dmaWriteDelay = p->dma_write_delay; - dmaReadFactor = p->dma_read_factor; - dmaWriteFactor = p->dma_write_factor; regsReset(); memcpy(&rom.perfectMatch, p->eaddr.bytes(), ETH_ADDR_LEN); -- cgit v1.2.3 From 63fef6b011fc2684a9ef04543c422a442df99932 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 22 Feb 2007 01:11:04 -0500 Subject: fix se compiling oops --HG-- extra : convert_revision : ce7ac94da0ed6bad457a8a9e4c949b0c3b09c2ae --- src/arch/sparc/isa/decoder.isa | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index e2d1707dd..3684cda69 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1009,6 +1009,7 @@ decode OP default Unknown::unknown() 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 0x81: FailUnimpl::siam(); } +#if FULL_SYSTEM // M5 special opcodes use the reserved IMPDEP2A opcode space 0x37: decode M5FUNC { // we have 7 bits of space here to play with... @@ -1019,6 +1020,9 @@ decode OP default Unknown::unknown() }}, No_OpClass, IsNonSpeculative); } +#else + 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); +#endif 0x38: Branch::jmpl({{ Addr target = Rs1 + Rs2_or_imm13; if(target & 0x3) -- cgit v1.2.3 From fa4c3d74fe7eb9627119d17542fbde18eb10423e Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 21 Feb 2007 22:14:11 -0800 Subject: Get rid of the ConsoleListener SimObject and just fold the relevant code directly into the SimConsole object. Now, you can easily turn off the listen port by just specifying 0 as the port. --HG-- extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0 --- configs/common/FSConfig.py | 2 +- src/dev/simconsole.cc | 229 +++++++++++++----------------------- src/dev/simconsole.hh | 76 ++++-------- src/python/m5/objects/SimConsole.py | 5 +- src/python/m5/objects/T1000.py | 6 +- 5 files changed, 116 insertions(+), 202 deletions(-) diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index c341b762a..2b13388d6 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -78,7 +78,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): read_only = True)) self.intrctrl = IntrControl() self.mem_mode = mem_mode - self.sim_console = SimConsole(listener=ConsoleListener(port=3456)) + self.sim_console = SimConsole() self.kernel = binary('vmlinux') self.pal = binary('ts_osfpal') self.console = binary('console') diff --git a/src/dev/simconsole.cc b/src/dev/simconsole.cc index 903368491..c6ff9c1c6 100644 --- a/src/dev/simconsole.cc +++ b/src/dev/simconsole.cc @@ -56,17 +56,31 @@ using namespace std; -//////////////////////////////////////////////////////////////////////// -// -// -SimConsole::Event::Event(SimConsole *c, int fd, int e) +/* + * Poll event for the listen socket + */ +SimConsole::ListenEvent::ListenEvent(SimConsole *c, int fd, int e) + : PollEvent(fd, e), cons(c) +{ +} + +void +SimConsole::ListenEvent::process(int revent) +{ + cons->accept(); +} + +/* + * Poll event for the data socket + */ +SimConsole::DataEvent::DataEvent(SimConsole *c, int fd, int e) : PollEvent(fd, e), cons(c) { } void -SimConsole::Event::process(int revent) +SimConsole::DataEvent::process(int revent) { if (revent & POLLIN) cons->data(); @@ -74,41 +88,76 @@ SimConsole::Event::process(int revent) cons->detach(); } -SimConsole::SimConsole(const string &name, ostream *os, int num) - : SimObject(name), event(NULL), number(num), in_fd(-1), out_fd(-1), - listener(NULL), txbuf(16384), rxbuf(16384), outfile(os) +/* + * SimConsole code + */ +SimConsole::SimConsole(const string &name, ostream *os, int num, int port) + : SimObject(name), listenEvent(NULL), dataEvent(NULL), number(num), + data_fd(-1), txbuf(16384), rxbuf(16384), outfile(os) #if TRACING_ON == 1 , linebuf(16384) #endif { if (outfile) outfile->setf(ios::unitbuf); + + if (port) + listen(port); } SimConsole::~SimConsole() { - close(); + if (data_fd != -1) + ::close(data_fd); + + if (listenEvent) + delete listenEvent; + + if (dataEvent) + delete dataEvent; } +/////////////////////////////////////////////////////////////////////// +// socket creation and console attach +// + void -SimConsole::close() +SimConsole::listen(int port) { - if (in_fd != -1) - ::close(in_fd); + while (!listener.listen(port, true)) { + DPRINTF(Console, + ": can't bind address console port %d inuse PID %d\n", + port, getpid()); + port++; + } + + int p1, p2; + p2 = name().rfind('.') - 1; + p1 = name().rfind('.', p2); + ccprintf(cerr, "Listening for %s connection on port %d\n", + name().substr(p1+1,p2-p1), port); - if (out_fd != in_fd && out_fd != -1) - ::close(out_fd); + listenEvent = new ListenEvent(this, listener.getfd(), POLLIN); + pollQueue.schedule(listenEvent); } void -SimConsole::attach(int in, int out, ConsoleListener *l) +SimConsole::accept() { - in_fd = in; - out_fd = out; - listener = l; + if (!listener.islistening()) + panic("%s: cannot accept a connection if not listening!", name()); + + int fd = listener.accept(true); + if (data_fd != -1) { + char message[] = "console already attached!\n"; + ::write(fd, message, sizeof(message)); + ::close(fd); + return; + } - event = new Event(this, in, POLLIN); - pollQueue.schedule(event); + data_fd = fd; + dataEvent = new DataEvent(this, data_fd, POLLIN); + pollQueue.schedule(dataEvent); stringstream stream; ccprintf(stream, "==== m5 slave console: Console %d ====", number); @@ -119,26 +168,23 @@ SimConsole::attach(int in, int out, ConsoleListener *l) write((const uint8_t *)stream.str().c_str(), stream.str().size()); - DPRINTFN("attach console %d\n", number); - txbuf.readall(out); + txbuf.readall(data_fd); } void SimConsole::detach() { - close(); - in_fd = -1; - out_fd = -1; - - pollQueue.remove(event); - - if (listener) { - listener->add(this); - listener = NULL; + if (data_fd != -1) { + ::close(data_fd); + data_fd = -1; } + pollQueue.remove(dataEvent); + delete dataEvent; + dataEvent = NULL; + DPRINTFN("detach console %d\n", number); } @@ -159,12 +205,12 @@ SimConsole::data() size_t SimConsole::read(uint8_t *buf, size_t len) { - if (in_fd < 0) + if (data_fd < 0) panic("Console not properly attached.\n"); size_t ret; do { - ret = ::read(in_fd, buf, len); + ret = ::read(data_fd, buf, len); } while (ret == -1 && errno == EINTR); @@ -183,12 +229,12 @@ SimConsole::read(uint8_t *buf, size_t len) size_t SimConsole::write(const uint8_t *buf, size_t len) { - if (out_fd < 0) + if (data_fd < 0) panic("Console not properly attached.\n"); size_t ret; for (;;) { - ret = ::write(out_fd, buf, len); + ret = ::write(data_fd, buf, len); if (ret >= 0) break; @@ -268,7 +314,7 @@ SimConsole::out(char c) txbuf.write(c); - if (out_fd >= 0) + if (data_fd >= 0) write(c); if (outfile) @@ -279,23 +325,11 @@ SimConsole::out(char c) } - -void -SimConsole::serialize(ostream &os) -{ -} - -void -SimConsole::unserialize(Checkpoint *cp, const std::string §ion) -{ -} - - BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole) - SimObjectParam listener; SimObjectParam intr_control; Param output; + Param port; Param append_name; Param number; @@ -303,9 +337,9 @@ END_DECLARE_SIM_OBJECT_PARAMS(SimConsole) BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole) - INIT_PARAM(listener, "console listener"), INIT_PARAM(intr_control, "interrupt controller"), INIT_PARAM(output, "file to dump output to"), + INIT_PARAM(port, ""), INIT_PARAM_DFLT(append_name, "append name() to filename", true), INIT_PARAM_DFLT(number, "console number", 0) @@ -322,100 +356,7 @@ CREATE_SIM_OBJECT(SimConsole) stream = simout.find(filename); } - SimConsole *console = new SimConsole(getInstanceName(), stream, number); - ((ConsoleListener *)listener)->add(console); - - return console; + return new SimConsole(getInstanceName(), stream, number, port); } REGISTER_SIM_OBJECT("SimConsole", SimConsole) - -//////////////////////////////////////////////////////////////////////// -// -// - -ConsoleListener::ConsoleListener(const string &name) - : SimObject(name), event(NULL) -{} - -ConsoleListener::~ConsoleListener() -{ - if (event) - delete event; -} - -void -ConsoleListener::Event::process(int revent) -{ - listener->accept(); -} - -/////////////////////////////////////////////////////////////////////// -// socket creation and console attach -// - -void -ConsoleListener::listen(int port) -{ - while (!listener.listen(port, true)) { - DPRINTF(Console, - ": can't bind address console port %d inuse PID %d\n", - port, getpid()); - port++; - } - - - int p1, p2; - p2 = name().rfind('.') - 1; - p1 = name().rfind('.', p2); - ccprintf(cerr, "Listening for %s connection on port %d\n", - name().substr(p1+1,p2-p1), port); - - event = new Event(this, listener.getfd(), POLLIN); - pollQueue.schedule(event); -} - -void -ConsoleListener::add(SimConsole *cons) -{ ConsoleList.push_back(cons);} - -void -ConsoleListener::accept() -{ - if (!listener.islistening()) - panic("%s: cannot accept a connection if not listening!", name()); - - int sfd = listener.accept(true); - if (sfd != -1) { - iter_t i = ConsoleList.begin(); - iter_t end = ConsoleList.end(); - if (i == end) { - close(sfd); - } else { - (*i)->attach(sfd, this); - i = ConsoleList.erase(i); - } - } -} - -BEGIN_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener) - - Param port; - -END_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener) - -BEGIN_INIT_SIM_OBJECT_PARAMS(ConsoleListener) - - INIT_PARAM_DFLT(port, "listen port", 3456) - -END_INIT_SIM_OBJECT_PARAMS(ConsoleListener) - -CREATE_SIM_OBJECT(ConsoleListener) -{ - ConsoleListener *listener = new ConsoleListener(getInstanceName()); - listener->listen(port); - - return listener; -} - -REGISTER_SIM_OBJECT("ConsoleListener", ConsoleListener) diff --git a/src/dev/simconsole.hh b/src/dev/simconsole.hh index ec99c6028..18a193493 100644 --- a/src/dev/simconsole.hh +++ b/src/dev/simconsole.hh @@ -53,29 +53,46 @@ class SimConsole : public SimObject Uart *uart; protected: - class Event : public PollEvent + class ListenEvent : public PollEvent { protected: SimConsole *cons; public: - Event(SimConsole *c, int fd, int e); + ListenEvent(SimConsole *c, int fd, int e); void process(int revent); }; - friend class Event; - Event *event; + friend class ListenEvent; + ListenEvent *listenEvent; + + class DataEvent : public PollEvent + { + protected: + SimConsole *cons; + + public: + DataEvent(SimConsole *c, int fd, int e); + void process(int revent); + }; + + friend class DataEvent; + DataEvent *dataEvent; protected: int number; - int in_fd; - int out_fd; - ConsoleListener *listener; + int data_fd; public: - SimConsole(const std::string &name, std::ostream *os, int num); + SimConsole(const std::string &name, std::ostream *os, int num, int port); ~SimConsole(); + protected: + ListenSocket listener; + + void listen(int port); + void accept(); + protected: CircleBuf txbuf; CircleBuf rxbuf; @@ -88,17 +105,13 @@ class SimConsole : public SimObject /////////////////////// // Terminal Interface - void attach(int fd, ConsoleListener *l = NULL) { attach(fd, fd, l); } - void attach(int in, int out, ConsoleListener *l = NULL); - void detach(); - void data(); - void close(); void read(uint8_t &c) { read(&c, 1); } size_t read(uint8_t *buf, size_t len); void write(uint8_t c) { write(&c, 1); } size_t write(const uint8_t *buf, size_t len); + void detach(); public: ///////////////// @@ -126,43 +139,6 @@ class SimConsole : public SimObject //Ask the console if data is available bool dataAvailable() { return !rxbuf.empty(); } - - virtual void serialize(std::ostream &os); - virtual void unserialize(Checkpoint *cp, const std::string §ion); -}; - -class ConsoleListener : public SimObject -{ - protected: - class Event : public PollEvent - { - protected: - ConsoleListener *listener; - - public: - Event(ConsoleListener *l, int fd, int e) - : PollEvent(fd, e), listener(l) {} - void process(int revent); - }; - - friend class Event; - Event *event; - - typedef std::list list_t; - typedef list_t::iterator iter_t; - list_t ConsoleList; - - protected: - ListenSocket listener; - - public: - ConsoleListener(const std::string &name); - ~ConsoleListener(); - - void add(SimConsole *cons); - - void accept(); - void listen(int port); }; #endif // __CONSOLE_HH__ diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py index bdd7f246d..dfad18eb6 100644 --- a/src/python/m5/objects/SimConsole.py +++ b/src/python/m5/objects/SimConsole.py @@ -1,14 +1,11 @@ from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -class ConsoleListener(SimObject): - type = 'ConsoleListener' - port = Param.TcpPort(3456, "listen port") class SimConsole(SimObject): type = 'SimConsole' append_name = Param.Bool(True, "append name() to filename") intr_control = Param.IntrControl(Parent.any, "interrupt controller") - listener = Param.ConsoleListener("console listener") + port = Param.TcpPort(3456, "listen port") number = Param.Int(0, "console number") output = Param.String('console', "file to dump output to") diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py index 3ab6d4283..aeca491c4 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/python/m5/objects/T1000.py @@ -3,7 +3,7 @@ from m5.proxy import * from Device import BasicPioDevice, IsaFake, BadAddr from Uart import Uart8250 from Platform import Platform -from SimConsole import SimConsole, ConsoleListener +from SimConsole import SimConsole class MmDisk(BasicPioDevice): @@ -69,11 +69,11 @@ class T1000(Platform): fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) #warn_access="Accessing SSI -- Unimplemented!") - hconsole = SimConsole(listener = ConsoleListener()) + hconsole = SimConsole() hvuart = Uart8250(pio_addr=0xfff0c2c000) htod = DumbTOD() - pconsole = SimConsole(listener = ConsoleListener()) + pconsole = SimConsole() puart0 = Uart8250(pio_addr=0x1f10000000) # Attach I/O devices to specified bus object. Can't do this -- cgit v1.2.3 From c003dda793b5cc6fb9d9953fa1477849ddc42944 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 21 Feb 2007 22:25:48 -0800 Subject: Make it easier to turn off the remote debugger --HG-- extra : convert_revision : d88784736df5f9b498770fb7e98f52715669c0e1 --- src/sim/system.cc | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/src/sim/system.cc b/src/sim/system.cc index f6febe4b1..1a87e1754 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -142,6 +142,7 @@ System::~System() } int rgdb_wait = -1; +int rgdb_enable = true; void System::setMemoryMode(MemoryMode mode) @@ -152,7 +153,9 @@ System::setMemoryMode(MemoryMode mode) bool System::breakpoint() { - return remoteGDB[0]->breakpoint(); + if (remoteGDB.size()) + return remoteGDB[0]->breakpoint(); + return false; } int @@ -174,22 +177,24 @@ System::registerThreadContext(ThreadContext *tc, int id) threadContexts[id] = tc; numcpus++; - RemoteGDB *rgdb = new RemoteGDB(this, tc); - GDBListener *gdbl = new GDBListener(rgdb, 7000 + id); - gdbl->listen(); - /** - * Uncommenting this line waits for a remote debugger to connect - * to the simulator before continuing. - */ - if (rgdb_wait != -1 && rgdb_wait == id) - gdbl->accept(); + if (rgdb_enable) { + RemoteGDB *rgdb = new RemoteGDB(this, tc); + GDBListener *gdbl = new GDBListener(rgdb, 7000 + id); + gdbl->listen(); + /** + * Uncommenting this line waits for a remote debugger to + * connect to the simulator before continuing. + */ + if (rgdb_wait != -1 && rgdb_wait == id) + gdbl->accept(); + + if (remoteGDB.size() <= id) { + remoteGDB.resize(id + 1); + } - if (remoteGDB.size() <= id) { - remoteGDB.resize(id + 1); + remoteGDB[id] = rgdb; } - remoteGDB[id] = rgdb; - return id; } @@ -210,7 +215,8 @@ System::replaceThreadContext(ThreadContext *tc, int id) } threadContexts[id] = tc; - remoteGDB[id]->replaceThreadContext(tc); + if (id < remoteGDB.size()) + remoteGDB[id]->replaceThreadContext(tc); } #if !FULL_SYSTEM -- cgit v1.2.3