From c145876cef258637ec30996d3f3c73e33fd58a4a Mon Sep 17 00:00:00 2001 From: Adrian Herrera Date: Tue, 3 Dec 2019 14:31:12 +0000 Subject: dev-arm: VExpress_GEM5_Base, add refclock 32KHz This patch adds the reference 32KHz clock to VExpress_GEM5_Base derived platforms. This is in preparation for supporting the SP805 Watchdog. I/O voltage domain and platform clock domain coupling is transferred to the __init__ method for correctness. Change-Id: Ic743fd986793f1e43b75fa60260c9b43b2737763 Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24204 Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/dev/arm/RealView.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index e65f118c1..e773096b7 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -1,4 +1,4 @@ -# Copyright (c) 2009-2019 ARM Limited +# Copyright (c) 2009-2020 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -959,8 +959,9 @@ Interrupts: return memories ### Off-chip devices ### - clock24MHz = SrcClockDomain(clock="24MHz", - voltage_domain=VoltageDomain(voltage="3.3V")) + io_voltage = VoltageDomain(voltage="3.3V") + clock32KHz = SrcClockDomain(clock="32kHz") + clock24MHz = SrcClockDomain(clock="24MHz") uart = [ Pl011(pio_addr=0x1c090000, int_num=37), @@ -995,11 +996,17 @@ Interrupts: self.rtc, self.pci_host, self.energy_ctrl, + self.clock32KHz, self.clock24MHz, self.vio[0], self.vio[1], ] + def __init__(self, **kwargs): + super(VExpress_GEM5_Base, self).__init__(**kwargs) + self.clock32KHz.voltage_domain = self.io_voltage + self.clock24MHz.voltage_domain = self.io_voltage + def attachPciDevice(self, device, *args, **kwargs): device.host = self.pci_host self._num_pci_dev += 1 -- cgit v1.2.3