From c5baffb5303e9c49d9d475e38783cdcf3391a9a4 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Wed, 12 Dec 2018 16:56:28 +0000
Subject: cpu: Fix usage of setArchVecElem

setArchVecElem should create a VecElemClass RegId, and not a VecRegClass.
Initializing a VecRegClass with three arguments makes it panic

Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15655
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/cpu/o3/cpu.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e5b8103ab..8f399e9f5 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1466,7 +1466,7 @@ FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
                                 const VecElem& val, ThreadID tid)
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
-                RegId(VecRegClass, reg_idx, ldx));
+                RegId(VecElemClass, reg_idx, ldx));
     setVecElem(phys_reg, val);
 }
 
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