From d1f9414e111b4b5e6d0f60ca64a415a47765e9e0 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Sun, 22 Apr 2007 14:39:39 -0400
Subject: Update configs to set the CPU clock properly.

--HG--
extra : convert_revision : 62fec666f987e9a9a441e319458908483cd2c5ff
---
 tests/configs/o3-timing-mp.py     | 3 ++-
 tests/configs/o3-timing.py        | 1 +
 tests/configs/simple-atomic-mp.py | 3 ++-
 tests/configs/simple-atomic.py    | 3 ++-
 tests/configs/simple-timing-mp.py | 3 ++-
 tests/configs/simple-timing.py    | 3 ++-
 6 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 331e2c569..1e414294c 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -73,6 +73,7 @@ for cpu in cpus:
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
+    cpu.clock = '2GHz'
 
 # connect memory to membus
 system.physmem.port = system.membus.port
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 5600d9f22..d20a7e0c8 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -40,6 +40,7 @@ class MyCache(BaseCache):
 cpu = DerivO3CPU(cpu_id=0)
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
+cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index f9e4e2767..e8000cd0a 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@ for cpu in cpus:
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
+    cpu.clock = '2GHz'
 
 # connect memory to membus
 system.physmem.port = system.membus.port
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index a8a876994..cc303886b 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
+system.cpu.clock = '2GHz'
 
 root = Root(system = system)
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 0d99d8714..a263bcf57 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@ for cpu in cpus:
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
+    cpu.clock = '2GHz'
 
 # connect memory to membus
 system.physmem.port = system.membus.port
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index d7d505a5a..6c4b8232f 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -44,5 +44,6 @@ system = System(cpu = cpu,
                 membus = Bus())
 system.physmem.port = system.membus.port
 cpu.connectMemPorts(system.membus)
+cpu.clock = '2GHz'
 
 root = Root(system = system)
-- 
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