From da20c0ec54d322cbffe3c7d0053ea4dc8be24d94 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 12 Jun 2008 00:58:13 -0400 Subject: X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports. --- src/dev/x86/PC.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py index 86ae4c3ba..4ba9e7a8a 100644 --- a/src/dev/x86/PC.py +++ b/src/dev/x86/PC.py @@ -50,6 +50,10 @@ class PC(Platform): # "Non-existant" port used for timing purposes by the linux kernel i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) + # Ports behind the pci config and data regsiters. These don't do anything, + # but the linux kernel fiddles with them anway. + behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) + # Serial port and console console = SimConsole() com_1 = Uart8250() @@ -59,6 +63,7 @@ class PC(Platform): def attachIO(self, bus): self.south_bridge.pio = bus.port self.i_dont_exist.pio = bus.port + self.behind_pci.pio = bus.port self.com_1.pio = bus.port self.pciconfig.pio = bus.default bus.responder_set = True -- cgit v1.2.3