From dc5eedd405c5e83e9ecce1fb13dee168acfda130 Mon Sep 17 00:00:00 2001
From: Iru Cai <mytbk920423@gmail.com>
Date: Sun, 12 May 2019 21:28:43 +0800
Subject: still cannot run fence+ift...

---
 src/cpu/o3/lsq_unit_impl.hh | 31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 80445e261..fb6d8cb54 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -124,12 +124,14 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
         return;
     }
 
-    if ( pkt->isSpec() && pkt->isRead() && (!pkt->isL1Hit()) ) {
-        DPRINTF(LSQUnit, "spec load miss for inst [sn:%lli], fence it.\n",
-                inst->seqNum);
-        inst->fenceDelay(true);
-    } else {
-        DPRINTF(LSQUnit, "spec load hit for inst [sn:%lli].\n");
+    if ( pkt->isSpec() ) {
+        if ( pkt->isRead() && (!pkt->isL1Hit()) ) {
+            DPRINTF(LSQUnit, "spec load miss for inst [sn:%lli], fence it.\n",
+                    inst->seqNum);
+            inst->fenceDelay(true);
+        } else {
+            DPRINTF(LSQUnit, "spec load hit for inst [sn:%lli].\n", inst->seqNum);
+        }
     }
 
     assert(!cpu->switchedOut());
@@ -1373,12 +1375,17 @@ LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
             "in this case, we will put it into ROB twice.");
 
     if (inst->fenceDelay()) {
-        DPRINTF(LSQUnit, "To write back a fence delayed spec load [sn:%lli].\n", inst->seqNum);
-        assert(pkt->isSpec());
-        inst->onlyWaitForFence(true);
-        inst->translationStarted(false);
-        inst->translationCompleted(false);
-        iewStage->instQueue.deferMemInst(inst);
+        if (pkt->isSpec()) {
+            DPRINTF(LSQUnit, "To write back a fence delayed spec load [sn:%lli].\n", inst->seqNum);
+            inst->onlyWaitForFence(true);
+            inst->translationStarted(false);
+            inst->translationCompleted(false);
+            iewStage->instQueue.deferMemInst(inst);
+        } else {
+            DPRINTF(LSQUnit, "inst [sn:%lli] inst->fenceDelay() && !pkt->isSpec()"
+                    "at LSQUnit::writeback, possibly due to IFT issue in gem5.\n", inst->seqNum);
+            inst->fenceDelay(false);
+        }
     } else if (!inst->isExecuted()) {
         inst->setExecuted();
 
-- 
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