From 57482491c5eeb3e52f2f29f5f56040445004cb43 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 13 Feb 2005 23:03:04 -0500 Subject: build mysql version if libraries exist add dprintf on alignment faults fix RR benchmark rcS script name Add Dual test without rcS script Update Monet to be closer to the real thing Fix p4/monet configs Add a way to read the DRIR register with at 32bit access for validation SConscript: build/SConstruct: always use mysql if the libraries are installed arch/alpha/alpha_memory.cc: Add a DPRINTF to print alignment faults when they happen dev/tsunami_cchip.cc: Add a way to read the DRIR for validation. --HG-- extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015 --- SConscript | 13 ++++++------- arch/alpha/alpha_memory.cc | 2 ++ build/SConstruct | 11 ----------- dev/tsunami_cchip.cc | 2 +- 4 files changed, 9 insertions(+), 19 deletions(-) diff --git a/SConscript b/SConscript index 187edadff..e49a507b8 100644 --- a/SConscript +++ b/SConscript @@ -28,6 +28,7 @@ import os import sys +from os.path import isdir # This file defines how to build a particular configuration of M5 # based on variable settings in the 'env' build environment. @@ -335,18 +336,16 @@ else: extra_libraries = [] env.Append(LIBS=['z']) -if env['USE_MYSQL']: +if isdir('/usr/lib64/mysql') or isdir('/usr/lib/mysql') or \ + isdir('/usr/local/lib/mysql'): + env.Append(LIBPATH=['/usr/lib64/mysql', '/usr/local/lib/mysql/', + '/usr/lib/mysql']) + env.Append(CPPPATH=['/usr/local/include/mysql', '/usr/include/mysql']) sources += mysql_sources env.Append(CPPDEFINES = 'USE_MYSQL') env.Append(CPPDEFINES = 'STATS_BINNING') - env.Append(CPPPATH=['/usr/local/include/mysql', '/usr/include/mysql']) - if os.path.isdir('/usr/lib64'): - env.Append(LIBPATH=['/usr/lib64/mysql']) - else: - env.Append(LIBPATH=['/usr/lib/mysql/']) env.Append(LIBS=['mysqlclient']) - ################################################### # # Special build rules. diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 81a1902a0..639abbeb8 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -501,6 +501,8 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const */ if (req->vaddr & (req->size - 1)) { fault(req, write ? MM_STAT_WR_MASK : 0); + DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, + req->size); return Alignment_Fault; } diff --git a/build/SConstruct b/build/SConstruct index 3d7db1db2..5c4ae94a1 100644 --- a/build/SConstruct +++ b/build/SConstruct @@ -101,23 +101,12 @@ configs_map = { 'KERNEL' : KernelConfig } -# Enable detailed full-system binning. -def MeasureOpt(env): - env.Replace(USE_MYSQL = True) - env.Append(CPPDEFINES = 'FS_MEASURE') - -# Enable MySql database output for stats. -def MySqlOpt(env): - env.Replace(USE_MYSQL = True) - # Disable FastAlloc object allocation. def NoFastAllocOpt(env): env.Append(CPPDEFINES = 'NO_FAST_ALLOC') # Configuration options map. options_map = { - 'MEASURE' : MeasureOpt, - 'MYSQL' : MySqlOpt, 'NO_FAST_ALLOC' : NoFastAllocOpt } diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 6bf4d8b57..2fb293fbf 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -176,7 +176,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) if (regnum == TSDEV_CC_DRIR) { warn("accessing DRIR with 32 bit read, " "hopefully your just reading this for timing"); - *(uint64_t*)data = drir; + *(uint32_t*)data = drir; } else panic("invalid access size(?) for tsunami register!\n"); return No_Fault; -- cgit v1.2.3 From b1ab7b53c337cd725fcddc03f1d91b11fe842c29 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 14 Feb 2005 18:54:38 -0500 Subject: output dir changes to python files util/pbs/job.py: pass output dir to m5 directly --HG-- extra : convert_revision : 00d1568bb2da3b3e646fc75b4884314bf4cb2d71 --- util/pbs/job.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/pbs/job.py b/util/pbs/job.py index 5eed0cd75..7c8d4bc16 100755 --- a/util/pbs/job.py +++ b/util/pbs/job.py @@ -134,7 +134,7 @@ if __name__ == '__main__': os.symlink(joinpath(jobdir, 'output'), 'status.out') - args = [ joinpath(basedir, 'm5'), joinpath(basedir, 'run.mpy') ] + args = [ joinpath(basedir, 'm5'), '-d', '%s' % jobdir, joinpath(basedir, 'run.mpy') ] if not len(args): sys.exit("no arguments") -- cgit v1.2.3 From 5e9bc06457923893d5acf049ab5d1dd621a865cc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 14 Feb 2005 20:22:27 -0500 Subject: Make it so we append jobs to the joblist in the for loop not outside of the loop so we get all of the jobs, not just the last one. util/pbs/send.py: fix indent --HG-- extra : convert_revision : eee9546b4945ff949fdfdf339fc95a23603b47d3 --- util/pbs/send.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/pbs/send.py b/util/pbs/send.py index 4daf15b45..b796cadbd 100755 --- a/util/pbs/send.py +++ b/util/pbs/send.py @@ -156,7 +156,7 @@ if not onlyecho: job.cleandir(jobdir) else: os.mkdir(jobdir) - jl.append(jobname) + jl.append(jobname) joblist = jl for jobname in joblist: -- cgit v1.2.3 From f4e2f0ea339d0b2524dde28c6bf903c06e97c948 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 14 Feb 2005 20:47:05 -0500 Subject: undoing change per nates request --HG-- extra : convert_revision : c5c2fd88dfd8d893da51c2b80907260ec14a7593 --- SConscript | 13 +++++++------ build/SConstruct | 11 +++++++++++ util/pbs/job.py | 2 +- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/SConscript b/SConscript index 8f7899134..19f84f913 100644 --- a/SConscript +++ b/SConscript @@ -28,7 +28,6 @@ import os import sys -from os.path import isdir # This file defines how to build a particular configuration of M5 # based on variable settings in the 'env' build environment. @@ -337,16 +336,18 @@ else: extra_libraries = [] env.Append(LIBS=['z']) -if isdir('/usr/lib64/mysql') or isdir('/usr/lib/mysql') or \ - isdir('/usr/local/lib/mysql'): - env.Append(LIBPATH=['/usr/lib64/mysql', '/usr/local/lib/mysql/', - '/usr/lib/mysql']) - env.Append(CPPPATH=['/usr/local/include/mysql', '/usr/include/mysql']) +if env['USE_MYSQL']: sources += mysql_sources env.Append(CPPDEFINES = 'USE_MYSQL') env.Append(CPPDEFINES = 'STATS_BINNING') + env.Append(CPPPATH=['/usr/local/include/mysql', '/usr/include/mysql']) + if os.path.isdir('/usr/lib64'): + env.Append(LIBPATH=['/usr/lib64/mysql']) + else: + env.Append(LIBPATH=['/usr/lib/mysql/']) env.Append(LIBS=['mysqlclient']) + ################################################### # # Special build rules. diff --git a/build/SConstruct b/build/SConstruct index 5c4ae94a1..3d7db1db2 100644 --- a/build/SConstruct +++ b/build/SConstruct @@ -101,12 +101,23 @@ configs_map = { 'KERNEL' : KernelConfig } +# Enable detailed full-system binning. +def MeasureOpt(env): + env.Replace(USE_MYSQL = True) + env.Append(CPPDEFINES = 'FS_MEASURE') + +# Enable MySql database output for stats. +def MySqlOpt(env): + env.Replace(USE_MYSQL = True) + # Disable FastAlloc object allocation. def NoFastAllocOpt(env): env.Append(CPPDEFINES = 'NO_FAST_ALLOC') # Configuration options map. options_map = { + 'MEASURE' : MeasureOpt, + 'MYSQL' : MySqlOpt, 'NO_FAST_ALLOC' : NoFastAllocOpt } diff --git a/util/pbs/job.py b/util/pbs/job.py index 7c8d4bc16..5eed0cd75 100755 --- a/util/pbs/job.py +++ b/util/pbs/job.py @@ -134,7 +134,7 @@ if __name__ == '__main__': os.symlink(joinpath(jobdir, 'output'), 'status.out') - args = [ joinpath(basedir, 'm5'), '-d', '%s' % jobdir, joinpath(basedir, 'run.mpy') ] + args = [ joinpath(basedir, 'm5'), joinpath(basedir, 'run.mpy') ] if not len(args): sys.exit("no arguments") -- cgit v1.2.3 From a24016c731a69c47e694458f7f564ef1630d34c1 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 17 Feb 2005 02:48:56 -0500 Subject: Several tweaks to make binning work in any simulation configuration so that we can always have binning on. base/statistics.cc: If we're binning, and there is no bin active at the time we check all stats stuff, create a bin. base/statistics.hh: FS_MEASURE doesn't exist anymore base/stats/text.cc: don't print out bin names if there is only one bin sim/process.cc: don't zero stats. It happens automatically. Don't activate the context at the time it is registered, instead activate the first context in a startup callback. sim/process.hh: Add startup callback to initialize the first exec context --HG-- extra : convert_revision : bcb23cdb184b0abf7cecd79902f8a59b50f71fe4 --- base/statistics.cc | 7 +++++++ base/statistics.hh | 2 +- base/stats/text.cc | 2 +- sim/process.cc | 23 ++++++++++++++--------- sim/process.hh | 2 ++ 5 files changed, 25 insertions(+), 11 deletions(-) diff --git a/base/statistics.cc b/base/statistics.cc index 6e3dae1ef..6f5caf1fe 100644 --- a/base/statistics.cc +++ b/base/statistics.cc @@ -286,6 +286,13 @@ check() Database::stats().sort(StatData::less); +#if defined(STATS_BINNING) + if (MainBin::curBin() == NULL) { + static MainBin mainBin("main bin"); + mainBin.activate(); + } +#endif + if (i == end) return; diff --git a/base/statistics.hh b/base/statistics.hh index 9ec26eb4d..667a0ed48 100644 --- a/base/statistics.hh +++ b/base/statistics.hh @@ -2184,7 +2184,7 @@ class SumNode : public Node * binned. If the typedef is NoBin, nothing is binned. If it is * MainBin, then all stats are binned under that Bin. */ -#if defined(FS_MEASURE) || defined(STATS_BINNING) +#if defined(STATS_BINNING) typedef MainBin DefaultBin; #else typedef NoBin DefaultBin; diff --git a/base/stats/text.cc b/base/stats/text.cc index f7e82a30f..8cc5ff65e 100644 --- a/base/stats/text.cc +++ b/base/stats/text.cc @@ -126,7 +126,7 @@ Text::output() using namespace Database; ccprintf(*stream, "\n---------- Begin Simulation Statistics ----------\n"); - if (bins().empty()) { + if (bins().empty() || bins().size() == 1) { stat_list_t::const_iterator i, end = stats().end(); for (i = stats().begin(); i != end; ++i) (*i)->visit(*this); diff --git a/sim/process.cc b/sim/process.cc index c725d3b1c..4d860c51d 100644 --- a/sim/process.cc +++ b/sim/process.cc @@ -88,8 +88,6 @@ Process::Process(const string &name, fd_map[i] = -1; } - num_syscalls = 0; - // other parameters will be initialized when the program is loaded } @@ -145,21 +143,28 @@ Process::registerExecContext(ExecContext *xc) execContexts.push_back(xc); if (myIndex == 0) { - // first exec context for this process... initialize & enable - // copy process's initial regs struct xc->regs = *init_regs; - - // mark this context as active. - // activate with zero delay so that we start ticking right - // away on cycle 0 - xc->activate(0); } // return CPU number to caller and increment available CPU count return myIndex; } +void +Process::startup() +{ + if (execContexts.empty()) + return; + + // first exec context for this process... initialize & enable + ExecContext *xc = execContexts[0]; + + // mark this context as active. + // activate with zero delay so that we start ticking right + // away on cycle 0 + xc->activate(0); +} void Process::replaceExecContext(ExecContext *xc, int xcIndex) diff --git a/sim/process.hh b/sim/process.hh index bb4829875..817ab656c 100644 --- a/sim/process.hh +++ b/sim/process.hh @@ -108,6 +108,8 @@ class Process : public SimObject int stdout_fd, int stderr_fd); + // post initialization startup + virtual void startup(); protected: FunctionalMemory *memory; -- cgit v1.2.3 From 5de3bba7589cc5c084af8e688a46f1b32566522f Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 17 Feb 2005 02:50:34 -0500 Subject: Make code more portable. sim/main.cc: basename is in libgen --HG-- extra : convert_revision : 1af6ff2f492b4deee9e56edfa5ee6ea235cd4eb0 --- sim/main.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/main.cc b/sim/main.cc index 1748294af..d4c31d5f2 100644 --- a/sim/main.cc +++ b/sim/main.cc @@ -31,6 +31,7 @@ /// #include #include +#include #include #include -- cgit v1.2.3 From cfe6ed7c484b62d07bae23c528f0e2e568cf0d65 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 17 Feb 2005 03:40:17 -0500 Subject: Fix compile on linux sim/main.cc: For some unknown reason linux's basename doesn't take a const char * --HG-- extra : convert_revision : 30289195881e16a05429f7025abab7914a9e3eb6 --- sim/main.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/main.cc b/sim/main.cc index d4c31d5f2..891931c2b 100644 --- a/sim/main.cc +++ b/sim/main.cc @@ -108,7 +108,7 @@ abortHandler(int sigtype) } /// Simulator executable name -const char *myProgName = ""; +char *myProgName = ""; /// Show brief help message. void -- cgit v1.2.3 From dd4220ec10e03db5743cfb5246696fd4c494829d Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 17 Feb 2005 14:02:03 -0500 Subject: rename the simple cpu's multiplier parameter. call it width. it makes more sense and is less confusing. cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: width is a better name than multiplier --HG-- extra : convert_revision : ea2fa4faa160f5657aece41df469bbc9f7244b21 --- cpu/simple_cpu/simple_cpu.cc | 29 +++++++++++++++-------------- cpu/simple_cpu/simple_cpu.hh | 14 ++++---------- 2 files changed, 19 insertions(+), 24 deletions(-) diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index f292b25a5..9079aba82 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -75,15 +75,15 @@ using namespace std; -SimpleCPU::TickEvent::TickEvent(SimpleCPU *c) - : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1) +SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) + : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w) { } void SimpleCPU::TickEvent::process() { - int count = multiplier; + int count = width; do { cpu->tick(); } while (--count > 0 && cpu->status() == Running); @@ -97,8 +97,7 @@ SimpleCPU::TickEvent::description() SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu) - : Event(&mainEventQueue), - cpu(_cpu) + : Event(&mainEventQueue), cpu(_cpu) { } @@ -125,7 +124,8 @@ SimpleCPU::SimpleCPU(const string &_name, MemInterface *icache_interface, MemInterface *dcache_interface, bool _def_reg, Tick freq, - bool _function_trace, Tick _function_trace_start) + bool _function_trace, Tick _function_trace_start, + int width) : BaseCPU(_name, /* number_of_threads */ 1, _def_reg, max_insts_any_thread, max_insts_all_threads, max_loads_any_thread, max_loads_all_threads, @@ -139,13 +139,14 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process, MemInterface *icache_interface, MemInterface *dcache_interface, bool _def_reg, - bool _function_trace, Tick _function_trace_start) + bool _function_trace, Tick _function_trace_start, + int width) : BaseCPU(_name, /* number_of_threads */ 1, _def_reg, max_insts_any_thread, max_insts_all_threads, max_loads_any_thread, max_loads_all_threads, _function_trace, _function_trace_start), #endif - tickEvent(this), xc(NULL), cacheCompletionEvent(this) + tickEvent(this, width), xc(NULL), cacheCompletionEvent(this) { _status = Idle; #ifdef FULL_SYSTEM @@ -841,7 +842,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) SimObjectParam dcache; Param defer_registration; - Param multiplier; + Param width; Param function_trace; Param function_trace_start; @@ -877,7 +878,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) INIT_PARAM_DFLT(defer_registration, "defer registration with system " "(for sampling)", false), - INIT_PARAM_DFLT(multiplier, "clock multiplier", 1), + INIT_PARAM_DFLT(width, "cpu width", 1), INIT_PARAM_DFLT(function_trace, "Enable function trace", false), INIT_PARAM_DFLT(function_trace_start, "Cycle to start function trace", 0) @@ -899,7 +900,8 @@ CREATE_SIM_OBJECT(SimpleCPU) (dcache) ? dcache->getInterface() : NULL, defer_registration, ticksPerSecond * mult, - function_trace, function_trace_start); + function_trace, function_trace_start, + width); #else cpu = new SimpleCPU(getInstanceName(), workload, @@ -908,12 +910,11 @@ CREATE_SIM_OBJECT(SimpleCPU) (icache) ? icache->getInterface() : NULL, (dcache) ? dcache->getInterface() : NULL, defer_registration, - function_trace, function_trace_start); + function_trace, function_trace_start, + width); #endif // FULL_SYSTEM - cpu->setTickMultiplier(multiplier); - return cpu; } diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index a81d6365b..731b3ddbc 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -69,9 +69,9 @@ class SimpleCPU : public BaseCPU struct TickEvent : public Event { SimpleCPU *cpu; - int multiplier; + int width; - TickEvent(SimpleCPU *c); + TickEvent(SimpleCPU *c, int w); void process(); const char *description(); }; @@ -94,12 +94,6 @@ class SimpleCPU : public BaseCPU tickEvent.squash(); } - public: - void setTickMultiplier(int multiplier) - { - tickEvent.multiplier = multiplier; - } - private: Trace::InstRecord *traceData; @@ -137,7 +131,7 @@ class SimpleCPU : public BaseCPU AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem, MemInterface *icache_interface, MemInterface *dcache_interface, bool _def_reg, Tick freq, - bool _function_trace, Tick _function_trace_start); + bool _function_trace, Tick _function_trace_start, int width); #else @@ -148,7 +142,7 @@ class SimpleCPU : public BaseCPU Counter max_loads_all_threads, MemInterface *icache_interface, MemInterface *dcache_interface, bool _def_reg, - bool _function_trace, Tick _function_trace_start); + bool _function_trace, Tick _function_trace_start, int width); #endif -- cgit v1.2.3 From f4d3f781f1a36d07700a2af98319b67b179f9e5d Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 17 Feb 2005 19:22:42 -0500 Subject: Include errno.h to fix compile errors in gcc 3.4 sim/main.cc: Include errno.h --HG-- extra : convert_revision : ff91579ae590b3c1d11f7468b71f295e6f3edd68 --- sim/main.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/main.cc b/sim/main.cc index 891931c2b..4352a90f4 100644 --- a/sim/main.cc +++ b/sim/main.cc @@ -31,6 +31,7 @@ /// #include #include +#include #include #include #include -- cgit v1.2.3 From 9b1e2db811f86d9911bacaad475d1fec70c4aecd Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 19 Feb 2005 11:46:41 -0500 Subject: Clean up CPU stuff and make it use params structs cpu/base_cpu.cc: cpu/base_cpu.hh: Convert the CPU stuff to use a params struct cpu/memtest/memtest.cc: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. Don't have any default parameters. cpu/memtest/memtest.hh: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. cpu/simple_cpu/simple_cpu.cc: Convert to use a params struct. remove default parameters cpu/simple_cpu/simple_cpu.hh: convert to use a params struct cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: this isn't really a cpu. don't derive from BaseCPU objects/MemTest.mpy: we only need one max_loads parameter sim/main.cc: Don't check for the number of CPUs since we may be doing something else going on. If we don't have anything to simulate, the simulator will exit anyway. --HG-- extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5 --- cpu/base_cpu.cc | 49 ++++++----------- cpu/base_cpu.hh | 31 ++++++----- cpu/memtest/memtest.cc | 49 +++++++---------- cpu/memtest/memtest.hh | 17 +++--- cpu/simple_cpu/simple_cpu.cc | 128 ++++++++++++++++--------------------------- cpu/simple_cpu/simple_cpu.hh | 34 +++++------- cpu/trace/opt_cpu.cc | 2 +- cpu/trace/opt_cpu.hh | 11 ++-- cpu/trace/trace_cpu.cc | 2 +- cpu/trace/trace_cpu.hh | 11 ++-- objects/MemTest.mpy | 5 +- sim/main.cc | 6 -- 12 files changed, 139 insertions(+), 206 deletions(-) diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc index 425ac8877..a17edd371 100644 --- a/cpu/base_cpu.cc +++ b/cpu/base_cpu.cc @@ -49,25 +49,12 @@ vector BaseCPU::cpuList; int maxThreadsPerCPU = 1; #ifdef FULL_SYSTEM -BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, - Counter max_insts_any_thread, - Counter max_insts_all_threads, - Counter max_loads_any_thread, - Counter max_loads_all_threads, - System *_system, Tick freq, - bool _function_trace, Tick _function_trace_start) - : SimObject(_name), frequency(freq), checkInterrupts(true), - deferRegistration(_def_reg), number_of_threads(_number_of_threads), - system(_system) +BaseCPU::BaseCPU(Params *p) + : SimObject(p->name), frequency(p->freq), checkInterrupts(true), + params(p), number_of_threads(p->numberOfThreads), system(p->system) #else -BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, - Counter max_insts_any_thread, - Counter max_insts_all_threads, - Counter max_loads_any_thread, - Counter max_loads_all_threads, - bool _function_trace, Tick _function_trace_start) - : SimObject(_name), deferRegistration(_def_reg), - number_of_threads(_number_of_threads) +BaseCPU::BaseCPU(Params *p) + : SimObject(p->name), params(p), number_of_threads(p->numberOfThreads) #endif { // add self to global list of CPUs @@ -84,12 +71,12 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, // // set up instruction-count-based termination events, if any // - if (max_insts_any_thread != 0) + if (p->max_insts_any_thread != 0) for (int i = 0; i < number_of_threads; ++i) - new SimExitEvent(comInstEventQueue[i], max_insts_any_thread, + new SimExitEvent(comInstEventQueue[i], p->max_insts_any_thread, "a thread reached the max instruction count"); - if (max_insts_all_threads != 0) { + if (p->max_insts_all_threads != 0) { // allocate & initialize shared downcounter: each event will // decrement this when triggered; simulation will terminate // when counter reaches 0 @@ -98,7 +85,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, for (int i = 0; i < number_of_threads; ++i) new CountedExitEvent(comInstEventQueue[i], "all threads reached the max instruction count", - max_insts_all_threads, *counter); + p->max_insts_all_threads, *counter); } // allocate per-thread load-based event queues @@ -109,12 +96,12 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, // // set up instruction-count-based termination events, if any // - if (max_loads_any_thread != 0) + if (p->max_loads_any_thread != 0) for (int i = 0; i < number_of_threads; ++i) - new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread, + new SimExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, "a thread reached the max load count"); - if (max_loads_all_threads != 0) { + if (p->max_loads_all_threads != 0) { // allocate & initialize shared downcounter: each event will // decrement this when triggered; simulation will terminate // when counter reaches 0 @@ -123,7 +110,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, for (int i = 0; i < number_of_threads; ++i) new CountedExitEvent(comLoadEventQueue[i], "all threads reached the max load count", - max_loads_all_threads, *counter); + p->max_loads_all_threads, *counter); } #ifdef FULL_SYSTEM @@ -132,18 +119,18 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, #endif functionTracingEnabled = false; - if (_function_trace) { + if (p->functionTrace) { functionTraceStream = simout.find(csprintf("ftrace.%s", name())); currentFunctionStart = currentFunctionEnd = 0; - functionEntryTick = _function_trace_start; + functionEntryTick = p->functionTraceStart; - if (_function_trace_start == 0) { + if (p->functionTraceStart == 0) { functionTracingEnabled = true; } else { Event *e = new EventWrapper(this, true); - e->schedule(_function_trace_start); + e->schedule(p->functionTraceStart); } } } @@ -162,7 +149,7 @@ BaseCPU::~BaseCPU() void BaseCPU::init() { - if (!deferRegistration) + if (!params->deferRegistration) registerExecContexts(); } diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh index baa956aa8..dd1c7ac58 100644 --- a/cpu/base_cpu.hh +++ b/cpu/base_cpu.hh @@ -90,28 +90,31 @@ class BaseCPU : public SimObject virtual void haltContext(int thread_num) {} public: - + struct Params + { + std::string name; + int numberOfThreads; + bool deferRegistration; + Counter max_insts_any_thread; + Counter max_insts_all_threads; + Counter max_loads_any_thread; + Counter max_loads_all_threads; + Tick freq; + bool functionTrace; + Tick functionTraceStart; #ifdef FULL_SYSTEM - BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg, - Counter max_insts_any_thread, Counter max_insts_all_threads, - Counter max_loads_any_thread, Counter max_loads_all_threads, - System *_system, Tick freq, - bool _function_trace = false, Tick _function_trace_start = 0); -#else - BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg, - Counter max_insts_any_thread = 0, - Counter max_insts_all_threads = 0, - Counter max_loads_any_thread = 0, - Counter max_loads_all_threads = 0, - bool _function_trace = false, Tick _function_trace_start = 0); + System *system; #endif + }; + + const Params *params; + BaseCPU(Params *params); virtual ~BaseCPU(); virtual void init(); virtual void regStats(); - bool deferRegistration; void registerExecContexts(); /// Prepare for another CPU to take over execution. Called by diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc index e967c79da..14b119880 100644 --- a/cpu/memtest/memtest.cc +++ b/cpu/memtest/memtest.cc @@ -36,6 +36,7 @@ #include "base/misc.hh" #include "base/statistics.hh" +#include "cpu/exec_context.hh" #include "cpu/memtest/memtest.hh" #include "mem/cache/base_cache.hh" #include "mem/functional_mem/main_memory.hh" @@ -59,10 +60,8 @@ MemTest::MemTest(const string &name, unsigned _percentSourceUnaligned, unsigned _percentDestUnaligned, Addr _traceAddr, - Counter max_loads_any_thread, - Counter max_loads_all_threads) - : BaseCPU(name, 1, true, 0, 0, max_loads_any_thread, - max_loads_all_threads), + Counter _max_loads) + : SimObject(name), tickEvent(this), cacheInterface(_cache_interface), mainMem(main_mem), @@ -74,12 +73,13 @@ MemTest::MemTest(const string &name, progressInterval(_progressInterval), nextProgressMessage(_progressInterval), percentSourceUnaligned(_percentSourceUnaligned), - percentDestUnaligned(percentDestUnaligned) + percentDestUnaligned(percentDestUnaligned), + maxLoads(_max_loads) { vector cmd; cmd.push_back("/bin/ls"); vector null_vec; - xc = new ExecContext(this ,0,mainMem,0); + xc = new ExecContext(NULL, 0, mainMem, 0); blockSize = cacheInterface->getBlockSize(); blockAddrMask = blockSize - 1; @@ -160,7 +160,8 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data) nextProgressMessage += progressInterval; } - comLoadEventQueue[0]->serviceEvents(numReads); + if (numReads >= maxLoads) + SimExit(curTick, "Maximum number of loads reached!"); break; case Write: @@ -402,8 +403,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest) Param percent_source_unaligned; Param percent_dest_unaligned; Param trace_addr; - Param max_loads_any_thread; - Param max_loads_all_threads; + Param max_loads; END_DECLARE_SIM_OBJECT_PARAMS(MemTest) @@ -413,23 +413,17 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest) INIT_PARAM(cache, "L1 cache"), INIT_PARAM(main_mem, "hierarchical memory"), INIT_PARAM(check_mem, "check memory"), - INIT_PARAM_DFLT(memory_size, "memory size", 65536), - INIT_PARAM_DFLT(percent_reads, "target read percentage", 65), - INIT_PARAM_DFLT(percent_copies, "target copy percentage", 0), - INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10), - INIT_PARAM_DFLT(progress_interval, - "progress report interval (in accesses)", 1000000), - INIT_PARAM_DFLT(percent_source_unaligned, "percent of copy source address " - "that are unaligned", 50), - INIT_PARAM_DFLT(percent_dest_unaligned, "percent of copy dest address " - "that are unaligned", 50), - INIT_PARAM_DFLT(trace_addr, "address to trace", 0), - INIT_PARAM_DFLT(max_loads_any_thread, - "terminate when any thread reaches this load count", - 0), - INIT_PARAM_DFLT(max_loads_all_threads, - "terminate when all threads have reached this load count", - 0) + INIT_PARAM(memory_size, "memory size"), + INIT_PARAM(percent_reads, "target read percentage"), + INIT_PARAM(percent_copies, "target copy percentage"), + INIT_PARAM(percent_uncacheable, "target uncacheable percentage"), + INIT_PARAM(progress_interval, "progress report interval (in accesses)"), + INIT_PARAM(percent_source_unaligned, + "percent of copy source address that are unaligned"), + INIT_PARAM(percent_dest_unaligned, + "percent of copy dest address that are unaligned"), + INIT_PARAM(trace_addr, "address to trace"), + INIT_PARAM(max_loads, "terminate when we have reached this load count") END_INIT_SIM_OBJECT_PARAMS(MemTest) @@ -440,8 +434,7 @@ CREATE_SIM_OBJECT(MemTest) check_mem, memory_size, percent_reads, percent_copies, percent_uncacheable, progress_interval, percent_source_unaligned, percent_dest_unaligned, - trace_addr, max_loads_any_thread, - max_loads_all_threads); + trace_addr, max_loads); } REGISTER_SIM_OBJECT("MemTest", MemTest) diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh index 43b17a713..45b2d24e8 100644 --- a/cpu/memtest/memtest.hh +++ b/cpu/memtest/memtest.hh @@ -26,20 +26,21 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __MEMTEST_HH__ -#define __MEMTEST_HH__ +#ifndef __CPU_MEMTEST_MEMTEST_HH__ +#define __CPU_MEMTEST_MEMTEST_HH__ #include #include "base/statistics.hh" -#include "cpu/base_cpu.hh" -#include "cpu/exec_context.hh" #include "mem/functional_mem/functional_memory.hh" #include "mem/mem_interface.hh" +#include "sim/eventq.hh" +#include "sim/sim_exit.hh" #include "sim/sim_object.hh" #include "sim/stats.hh" -class MemTest : public BaseCPU +class ExecContext; +class MemTest : public SimObject { public: @@ -55,8 +56,7 @@ class MemTest : public BaseCPU unsigned _percentSourceUnaligned, unsigned _percentDestUnaligned, Addr _traceAddr, - Counter max_loads_any_thread, - Counter max_loads_all_threads); + Counter _max_loads); // register statistics virtual void regStats(); @@ -116,6 +116,7 @@ class MemTest : public BaseCPU Tick noResponseCycles; uint64_t numReads; + uint64_t maxLoads; Stats::Scalar<> numReadsStat; Stats::Scalar<> numWritesStat; Stats::Scalar<> numCopiesStat; @@ -146,7 +147,7 @@ class MemCompleteEvent : public Event virtual const char *description(); }; -#endif // __MEMTEST_HH__ +#endif // __CPU_MEMTEST_MEMTEST_HH__ diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 9079aba82..044ee9b9d 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -112,54 +112,22 @@ SimpleCPU::CacheCompletionEvent::description() return "SimpleCPU cache completion event"; } -#ifdef FULL_SYSTEM -SimpleCPU::SimpleCPU(const string &_name, - System *_system, - Counter max_insts_any_thread, - Counter max_insts_all_threads, - Counter max_loads_any_thread, - Counter max_loads_all_threads, - AlphaITB *itb, AlphaDTB *dtb, - FunctionalMemory *mem, - MemInterface *icache_interface, - MemInterface *dcache_interface, - bool _def_reg, Tick freq, - bool _function_trace, Tick _function_trace_start, - int width) - : BaseCPU(_name, /* number_of_threads */ 1, _def_reg, - max_insts_any_thread, max_insts_all_threads, - max_loads_any_thread, max_loads_all_threads, - _system, freq, _function_trace, _function_trace_start), -#else -SimpleCPU::SimpleCPU(const string &_name, Process *_process, - Counter max_insts_any_thread, - Counter max_insts_all_threads, - Counter max_loads_any_thread, - Counter max_loads_all_threads, - MemInterface *icache_interface, - MemInterface *dcache_interface, - bool _def_reg, - bool _function_trace, Tick _function_trace_start, - int width) - : BaseCPU(_name, /* number_of_threads */ 1, _def_reg, - max_insts_any_thread, max_insts_all_threads, - max_loads_any_thread, max_loads_all_threads, - _function_trace, _function_trace_start), -#endif - tickEvent(this, width), xc(NULL), cacheCompletionEvent(this) +SimpleCPU::SimpleCPU(Params *p) + : BaseCPU(p), tickEvent(this, p->width), xc(NULL), + cacheCompletionEvent(this) { _status = Idle; #ifdef FULL_SYSTEM - xc = new ExecContext(this, 0, system, itb, dtb, mem); + xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); // initialize CPU, including PC TheISA::initCPU(&xc->regs); #else - xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0); + xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); #endif // !FULL_SYSTEM - icacheInterface = icache_interface; - dcacheInterface = dcache_interface; + icacheInterface = p->icache_interface; + dcacheInterface = p->dcache_interface; memReq = new MemReq(); memReq->xc = xc; @@ -850,71 +818,67 @@ END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) - INIT_PARAM_DFLT(max_insts_any_thread, - "terminate when any thread reaches this inst count", - 0), - INIT_PARAM_DFLT(max_insts_all_threads, - "terminate when all threads have reached this inst count", - 0), - INIT_PARAM_DFLT(max_loads_any_thread, - "terminate when any thread reaches this load count", - 0), - INIT_PARAM_DFLT(max_loads_all_threads, - "terminate when all threads have reached this load count", - 0), + INIT_PARAM(max_insts_any_thread, + "terminate when any thread reaches this inst count"), + INIT_PARAM(max_insts_all_threads, + "terminate when all threads have reached this inst count"), + INIT_PARAM(max_loads_any_thread, + "terminate when any thread reaches this load count"), + INIT_PARAM(max_loads_all_threads, + "terminate when all threads have reached this load count"), #ifdef FULL_SYSTEM INIT_PARAM(itb, "Instruction TLB"), INIT_PARAM(dtb, "Data TLB"), INIT_PARAM(mem, "memory"), INIT_PARAM(system, "system object"), - INIT_PARAM_DFLT(mult, "system clock multiplier", 1), + INIT_PARAM(mult, "system clock multiplier"), #else INIT_PARAM(workload, "processes to run"), #endif // FULL_SYSTEM - INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL), - INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL), - INIT_PARAM_DFLT(defer_registration, "defer registration with system " - "(for sampling)", false), - - INIT_PARAM_DFLT(width, "cpu width", 1), - INIT_PARAM_DFLT(function_trace, "Enable function trace", false), - INIT_PARAM_DFLT(function_trace_start, "Cycle to start function trace", 0) + INIT_PARAM(icache, "L1 instruction cache object"), + INIT_PARAM(dcache, "L1 data cache object"), + INIT_PARAM(defer_registration, "defer system registration (for sampling)"), + INIT_PARAM(width, "cpu width"), + INIT_PARAM(function_trace, "Enable function trace"), + INIT_PARAM(function_trace_start, "Cycle to start function trace") END_INIT_SIM_OBJECT_PARAMS(SimpleCPU) CREATE_SIM_OBJECT(SimpleCPU) { - SimpleCPU *cpu; #ifdef FULL_SYSTEM if (mult != 1) panic("processor clock multiplier must be 1\n"); +#endif - cpu = new SimpleCPU(getInstanceName(), system, - max_insts_any_thread, max_insts_all_threads, - max_loads_any_thread, max_loads_all_threads, - itb, dtb, mem, - (icache) ? icache->getInterface() : NULL, - (dcache) ? dcache->getInterface() : NULL, - defer_registration, - ticksPerSecond * mult, - function_trace, function_trace_start, - width); -#else - - cpu = new SimpleCPU(getInstanceName(), workload, - max_insts_any_thread, max_insts_all_threads, - max_loads_any_thread, max_loads_all_threads, - (icache) ? icache->getInterface() : NULL, - (dcache) ? dcache->getInterface() : NULL, - defer_registration, - function_trace, function_trace_start, - width); + SimpleCPU::Params *params = new SimpleCPU::Params(); + params->name = getInstanceName(); + params->numberOfThreads = 1; + params->max_insts_any_thread = max_insts_any_thread; + params->max_insts_all_threads = max_insts_all_threads; + params->max_loads_any_thread = max_loads_any_thread; + params->max_loads_all_threads = max_loads_all_threads; + params->deferRegistration = defer_registration; + params->freq = ticksPerSecond; + params->functionTrace = function_trace; + params->functionTraceStart = function_trace_start; + params->icache_interface = (icache) ? icache->getInterface() : NULL; + params->dcache_interface = (dcache) ? dcache->getInterface() : NULL; + params->width = width; -#endif // FULL_SYSTEM +#ifdef FULL_SYSTEM + params->itb = itb; + params->dtb = dtb; + params->mem = mem; + params->system = system; +#else + params->process = workload; +#endif + SimpleCPU *cpu = new SimpleCPU(params); return cpu; } diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 731b3ddbc..0283545f4 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -122,32 +122,24 @@ class SimpleCPU : public BaseCPU } }; + public: + struct Params : public BaseCPU::Params + { + MemInterface *icache_interface; + MemInterface *dcache_interface; + int width; #ifdef FULL_SYSTEM - - SimpleCPU(const std::string &_name, - System *_system, - Counter max_insts_any_thread, Counter max_insts_all_threads, - Counter max_loads_any_thread, Counter max_loads_all_threads, - AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem, - MemInterface *icache_interface, MemInterface *dcache_interface, - bool _def_reg, Tick freq, - bool _function_trace, Tick _function_trace_start, int width); - + AlphaITB *itb; + AlphaDTB *dtb; + FunctionalMemory *mem; #else - - SimpleCPU(const std::string &_name, Process *_process, - Counter max_insts_any_thread, - Counter max_insts_all_threads, - Counter max_loads_any_thread, - Counter max_loads_all_threads, - MemInterface *icache_interface, MemInterface *dcache_interface, - bool _def_reg, - bool _function_trace, Tick _function_trace_start, int width); - + Process *process; #endif - + }; + SimpleCPU(Params *params); virtual ~SimpleCPU(); + public: // execution context ExecContext *xc; diff --git a/cpu/trace/opt_cpu.cc b/cpu/trace/opt_cpu.cc index 77211e382..15b53d46e 100644 --- a/cpu/trace/opt_cpu.cc +++ b/cpu/trace/opt_cpu.cc @@ -48,7 +48,7 @@ OptCPU::OptCPU(const string &name, int block_size, int cache_size, int _assoc) - : BaseCPU(name, 1, true), tickEvent(this), trace(_trace), + : SimObject(name), tickEvent(this), trace(_trace), numBlks(cache_size/block_size), assoc(_assoc), numSets(numBlks/assoc), setMask(numSets - 1) { diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh index 847147b3c..7f6aa3e18 100644 --- a/cpu/trace/opt_cpu.hh +++ b/cpu/trace/opt_cpu.hh @@ -32,14 +32,14 @@ * trace to access a fully associative cache with optimal replacement. */ -#ifndef __OPT_CPU_HH__ -#define __OPT_CPU_HH__ +#ifndef __CPU_TRACE_OPT_CPU_HH__ +#define __CPU_TRACE_OPT_CPU_HH__ #include -#include "cpu/base_cpu.hh" #include "mem/mem_req.hh" // for MemReqPtr #include "sim/eventq.hh" // for Event +#include "sim/sim_object.hh" // Forward Declaration class MemTraceReader; @@ -47,8 +47,9 @@ class MemTraceReader; /** * A CPU object to simulate a fully-associative cache with optimal replacement. */ -class OptCPU : public BaseCPU +class OptCPU : public SimObject { + private: typedef int RefIndex; typedef std::vector L3Table; @@ -219,4 +220,4 @@ class OptCPU : public BaseCPU void tick(); }; -#endif +#endif // __CPU_TRACE_OPT_CPU_HH__ diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc index f1160337a..1902d0be4 100644 --- a/cpu/trace/trace_cpu.cc +++ b/cpu/trace/trace_cpu.cc @@ -47,7 +47,7 @@ TraceCPU::TraceCPU(const string &name, MemInterface *icache_interface, MemInterface *dcache_interface, MemTraceReader *data_trace) - : BaseCPU(name, 4, true), icacheInterface(icache_interface), + : SimObject(name), icacheInterface(icache_interface), dcacheInterface(dcache_interface), dataTrace(data_trace), outstandingRequests(0), tickEvent(this) { diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh index 1711646a8..cdac4bb4f 100644 --- a/cpu/trace/trace_cpu.hh +++ b/cpu/trace/trace_cpu.hh @@ -32,14 +32,14 @@ * provided memory hierarchy. */ -#ifndef __TRACE_CPU_HH__ -#define __TRACE_CPU_HH__ +#ifndef __CPU_TRACE_TRACE_CPU_HH__ +#define __CPU_TRACE_TRACE_CPU_HH__ #include -#include "cpu/base_cpu.hh" #include "mem/mem_req.hh" // for MemReqPtr #include "sim/eventq.hh" // for Event +#include "sim/sim_object.hh" // Forward declaration. class MemInterface; @@ -48,8 +48,9 @@ class MemTraceReader; /** * A cpu object for running memory traces through a memory hierarchy. */ -class TraceCPU : public BaseCPU +class TraceCPU : public SimObject { + private: /** Interface for instruction trace requests, if any. */ MemInterface *icacheInterface; /** Interface for data trace requests, if any. */ @@ -133,5 +134,5 @@ class TraceCompleteEvent : public Event virtual const char *description(); }; -#endif //__TRACE_CPU_HH__ +#endif // __CPU_TRACE_TRACE_CPU_HH__ diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy index 1ec33a30c..af14ed9c3 100644 --- a/objects/MemTest.mpy +++ b/objects/MemTest.mpy @@ -3,10 +3,7 @@ simobj MemTest(SimObject): cache = Param.BaseCache("L1 cache") check_mem = Param.FunctionalMemory("check memory") main_mem = Param.FunctionalMemory("hierarchical memory") - max_loads_all_threads = Param.Counter(0, - "terminate when all threads have reached this load count") - max_loads_any_thread = Param.Counter(0, - "terminate when any thread reaches this load count") + max_loads = Param.Counter("number of loads to execute") memory_size = Param.Int(65536, "memory size") percent_copies = Param.Percent(0, "target copy percentage") percent_dest_unaligned = Param.Percent(50, diff --git a/sim/main.cc b/sim/main.cc index 4352a90f4..c15d24453 100644 --- a/sim/main.cc +++ b/sim/main.cc @@ -402,12 +402,6 @@ main(int argc, char **argv) // Reset to put the stats in a consistent state. Stats::reset(); - // Nothing to simulate if we don't have at least one CPU somewhere. - if (BaseCPU::numSimulatedCPUs() == 0) { - cerr << "Fatal: no CPUs to simulate." << endl; - exit(1); - } - warn("Entering event queue. Starting simulation...\n"); SimStartup(); while (!mainEventQueue.empty()) { -- cgit v1.2.3 From 92ed0dffc0ee71e3874c0a32734cf442a50c20c4 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 21 Feb 2005 17:32:57 -0500 Subject: formatting fixes --HG-- extra : convert_revision : 8b9bfed29b66e8bce11448f175273f5ebb6876b2 --- dev/tsunami.hh | 35 ++++++++++++------------ dev/tsunami_io.cc | 1 - dev/tsunami_io.hh | 79 ++++++++++++++++++++++++++----------------------------- 3 files changed, 55 insertions(+), 60 deletions(-) diff --git a/dev/tsunami.hh b/dev/tsunami.hh index d7c549e90..7722c8417 100644 --- a/dev/tsunami.hh +++ b/dev/tsunami.hh @@ -32,8 +32,8 @@ * retains pointers to all its children so the children can communicate. */ -#ifndef __TSUNAMI_HH__ -#define __TSUNAMI_HH__ +#ifndef __DEV_TSUNAMI_HH__ +#define __DEV_TSUNAMI_HH__ #include "dev/platform.hh" @@ -56,7 +56,6 @@ class System; class Tsunami : public Platform { public: - /** Max number of CPUs in a Tsunami */ static const int Max_CPUs = 64; @@ -67,15 +66,15 @@ class Tsunami : public Platform TsunamiIO *io; /** Pointer to the Tsunami CChip. - * The chip contains some configuration information and - * all the interrupt mask and status registers - */ + * The chip contains some configuration information and + * all the interrupt mask and status registers + */ TsunamiCChip *cchip; /** Pointer to the Tsunami PChip. - * The pchip is the interface to the PCI bus, in our case - * it does not have to do much. - */ + * The pchip is the interface to the PCI bus, in our case + * it does not have to do much. + */ TsunamiPChip *pchip; int intr_sum_type[Tsunami::Max_CPUs]; @@ -83,12 +82,12 @@ class Tsunami : public Platform public: /** - * Constructor for the Tsunami Class. - * @param name name of the object - * @param con pointer to the console - * @param intrcontrol pointer to the interrupt controller - * @param intrFreq frequency that interrupts happen - */ + * Constructor for the Tsunami Class. + * @param name name of the object + * @param con pointer to the console + * @param intrcontrol pointer to the interrupt controller + * @param intrFreq frequency that interrupts happen + */ Tsunami(const std::string &name, System *s, IntrControl *intctrl, PciConfigAll *pci, int intrFreq); @@ -96,7 +95,7 @@ class Tsunami : public Platform * Return the interrupting frequency to AlphaAccess * @return frequency of RTC interrupts */ - virtual Tick intrFrequency(); + virtual Tick intrFrequency(); /** * Cause the cpu to post a serial interrupt to the CPU. @@ -120,7 +119,7 @@ class Tsunami : public Platform virtual Addr pciToDma(Addr pciAddr) const; - /** + /** * Serialize this object to the given output stream. * @param os The stream to serialize to. */ @@ -134,4 +133,4 @@ class Tsunami : public Platform virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -#endif // __TSUNAMI_HH__ +#endif // __DEV_TSUNAMI_HH__ diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 94a951d2c..6c9195bff 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -67,7 +67,6 @@ TsunamiIO::RTCEvent::process() schedule(curTick + ticksPerSecond/RTC_RATE); //Actually interrupt the processor here tsunami->cchip->postRTC(); - } const char * diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index d507355c3..a9f044ec9 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -30,8 +30,8 @@ * Tsunami Fake I/O Space mapping including RTC/timer interrupts */ -#ifndef __TSUNAMI_DMA_HH__ -#define __TSUNAMI_DMA_HH__ +#ifndef __DEV_TSUNAMI_IO_HH__ +#define __DEV_TSUNAMI_IO_HH__ #include "dev/io_device.hh" #include "base/range.hh" @@ -56,9 +56,11 @@ class TsunamiIO : public PioDevice struct tm tm; - /** In Tsunami RTC only has two i/o ports one for data and one for address, - * so you write the address and then read/write the data. This store the - * address you are going to be reading from on a read. + /** + * In Tsunami RTC only has two i/o ports one for data and one for + * address, so you write the address and then read/write the + * data. This store the address you are going to be reading from + * on a read. */ uint8_t RTCAddress; @@ -132,38 +134,37 @@ class TsunamiIO : public PioDevice class RTCEvent : public Event { protected: - /** A pointer back to tsunami to create interrupt the processor. */ - Tsunami* tsunami; + /** A pointer back to tsunami to create interrupt the processor. */ + Tsunami* tsunami; public: - /** RTC Event initializes the RTC event by scheduling an event - * RTC_RATE times pre second. */ - RTCEvent(Tsunami* t); - - /** - * Interrupth the processor and reschedule the event. - * */ - virtual void process(); - - /** - * Return a description of this event. - * @return a description - */ - virtual const char *description(); - - /** - * Serialize this object to the given output stream. - * @param os The stream to serialize to. - */ - virtual void serialize(std::ostream &os); - - - /** - * Reconstruct the state of this object from a checkpoint. - * @param cp The checkpoint use. - * @param section The section name of this object - */ - virtual void unserialize(Checkpoint *cp, const std::string §ion); - }; + /** RTC Event initializes the RTC event by scheduling an event + * RTC_RATE times pre second. */ + RTCEvent(Tsunami* t); + + /** + * Interrupth the processor and reschedule the event. + */ + virtual void process(); + + /** + * Return a description of this event. + * @return a description + */ + virtual const char *description(); + + /** + * Serialize this object to the given output stream. + * @param os The stream to serialize to. + */ + virtual void serialize(std::ostream &os); + + /** + * Reconstruct the state of this object from a checkpoint. + * @param cp The checkpoint use. + * @param section The section name of this object + */ + virtual void unserialize(Checkpoint *cp, const std::string §ion); + }; /** uip UpdateInProgess says that the rtc is updating, but we just fake it * by alternating it on every read of the bit since we are going to @@ -219,7 +220,6 @@ class TsunamiIO : public PioDevice */ uint32_t timerData; - public: /** * Return the freqency of the RTC @@ -227,7 +227,6 @@ class TsunamiIO : public PioDevice */ Tick frequency() const { return RTC_RATE; } - /** * Initialize all the data for devices supported by Tsunami I/O. * @param name name of this device. @@ -279,7 +278,6 @@ class TsunamiIO : public PioDevice */ virtual void serialize(std::ostream &os); - /** * Reconstruct the state of this object from a checkpoint. * @param cp The checkpoint use. @@ -287,8 +285,7 @@ class TsunamiIO : public PioDevice */ virtual void unserialize(Checkpoint *cp, const std::string §ion); - Tick cacheAccess(MemReqPtr &req); }; -#endif // __TSUNAMI_IO_HH__ +#endif // __DEV_TSUNAMI_IO_HH__ -- cgit v1.2.3 -- cgit v1.2.3