From ee54ad318a63e868ab10bbc1b714bbb8209a11da Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 30 Jun 2007 17:45:58 -0700 Subject: Event descriptions should not end in "event" (they function as adjectives not nouns) --HG-- extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb --- src/arch/mips/regfile/misc_regfile.cc | 2 +- src/cpu/base.cc | 2 +- src/cpu/o3/commit_impl.hh | 2 +- src/cpu/o3/cpu.cc | 6 +++--- src/cpu/o3/inst_queue_impl.hh | 2 +- src/cpu/o3/lsq_unit_impl.hh | 2 +- src/cpu/ozone/back_end_impl.hh | 4 ++-- src/cpu/ozone/cpu_impl.hh | 2 +- src/cpu/ozone/inorder_back_end_impl.hh | 2 +- src/cpu/ozone/inst_queue_impl.hh | 2 +- src/cpu/ozone/lsq_unit_impl.hh | 2 +- src/cpu/ozone/lw_back_end_impl.hh | 2 +- src/cpu/ozone/lw_lsq_impl.hh | 2 +- src/cpu/quiesce_event.cc | 2 +- src/cpu/simple/atomic.cc | 2 +- src/cpu/simple/timing.hh | 6 +++--- src/cpu/trace/opt_cpu.cc | 2 +- src/cpu/trace/trace_cpu.cc | 2 +- src/dev/ethertap.hh | 2 +- src/dev/uart8250.cc | 2 +- src/mem/bridge.hh | 2 +- 21 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index c97d93cf9..71be3adf9 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -357,7 +357,7 @@ MiscRegFile::CP0Event::process() const char * MiscRegFile::CP0Event::description() { - return "Coprocessor-0 event"; + return "Coprocessor-0"; } void diff --git a/src/cpu/base.cc b/src/cpu/base.cc index f86313da0..cf007a06b 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -91,7 +91,7 @@ CPUProgressEvent::process() const char * CPUProgressEvent::description() { - return "CPU Progress event"; + return "CPU Progress"; } #if FULL_SYSTEM diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 9411c6c62..f263383ae 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -67,7 +67,7 @@ template const char * DefaultCommit::TrapEvent::description() { - return "Trap event"; + return "Trap"; } template diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 6a3eb9c43..2bf8f9832 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -83,7 +83,7 @@ template const char * FullO3CPU::TickEvent::description() { - return "FullO3CPU tick event"; + return "FullO3CPU tick"; } template @@ -112,7 +112,7 @@ template const char * FullO3CPU::ActivateThreadEvent::description() { - return "FullO3CPU \"Activate Thread\" event"; + return "FullO3CPU \"Activate Thread\""; } template @@ -144,7 +144,7 @@ template const char * FullO3CPU::DeallocateContextEvent::description() { - return "FullO3CPU \"Deallocate Context\" event"; + return "FullO3CPU \"Deallocate Context\""; } template diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index bdf5f07aa..99bffe1a6 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -60,7 +60,7 @@ template const char * InstructionQueue::FUCompletion::description() { - return "Functional unit completion event"; + return "Functional unit completion"; } template diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 91e616589..810a6d29f 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -69,7 +69,7 @@ template const char * LSQUnit::WritebackEvent::description() { - return "Store writeback event"; + return "Store writeback"; } template diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh index 4078699fe..27146ecf0 100644 --- a/src/cpu/ozone/back_end_impl.hh +++ b/src/cpu/ozone/back_end_impl.hh @@ -583,7 +583,7 @@ template const char * BackEnd::LdWritebackEvent::description() { - return "Load writeback event"; + return "Load writeback"; } @@ -603,7 +603,7 @@ template const char * BackEnd::DCacheCompletionEvent::description() { - return "Cache completion event"; + return "Cache completion"; } template diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index d1214223b..d73e5768a 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -84,7 +84,7 @@ template const char * OzoneCPU::TickEvent::description() { - return "OzoneCPU tick event"; + return "OzoneCPU tick"; } template diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 8d7ebb60e..c57fa0200 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -540,5 +540,5 @@ template const char * InorderBackEnd::DCacheCompletionEvent::description() { - return "DCache completion event"; + return "DCache completion"; } diff --git a/src/cpu/ozone/inst_queue_impl.hh b/src/cpu/ozone/inst_queue_impl.hh index ea9d03c0d..461c7eb0f 100644 --- a/src/cpu/ozone/inst_queue_impl.hh +++ b/src/cpu/ozone/inst_queue_impl.hh @@ -64,7 +64,7 @@ template const char * InstQueue::FUCompletion::description() { - return "Functional unit completion event"; + return "Functional unit completion"; } #endif template diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh index c46eb90be..e08e54835 100644 --- a/src/cpu/ozone/lsq_unit_impl.hh +++ b/src/cpu/ozone/lsq_unit_impl.hh @@ -62,7 +62,7 @@ template const char * OzoneLSQ::StoreCompletionEvent::description() { - return "LSQ store completion event"; + return "LSQ store completion"; } template diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index c0a9cad24..f84bda348 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -121,7 +121,7 @@ template const char * LWBackEnd::TrapEvent::description() { - return "Trap event"; + return "Trap"; } template diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index eefc0df83..e3000288c 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -57,7 +57,7 @@ template const char * OzoneLWLSQ::WritebackEvent::description() { - return "Store writeback event"; + return "Store writeback"; } template diff --git a/src/cpu/quiesce_event.cc b/src/cpu/quiesce_event.cc index fa79e6d1e..3495a0e52 100644 --- a/src/cpu/quiesce_event.cc +++ b/src/cpu/quiesce_event.cc @@ -47,5 +47,5 @@ EndQuiesceEvent::process() const char* EndQuiesceEvent::description() { - return "End Quiesce Event."; + return "End Quiesce"; } diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index bcd6662c8..8e8da2fa2 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -57,7 +57,7 @@ AtomicSimpleCPU::TickEvent::process() const char * AtomicSimpleCPU::TickEvent::description() { - return "AtomicSimpleCPU tick event"; + return "AtomicSimpleCPU tick"; } Port * diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 39958bfb6..ba194b3fa 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -101,7 +101,7 @@ class TimingSimpleCPU : public BaseSimpleCPU TickEvent(TimingSimpleCPU *_cpu) :Event(&mainEventQueue), cpu(_cpu) {} - const char *description() { return "Timing CPU clock event"; } + const char *description() { return "Timing CPU tick"; } void schedule(PacketPtr _pkt, Tick t); }; @@ -127,7 +127,7 @@ class TimingSimpleCPU : public BaseSimpleCPU ITickEvent(TimingSimpleCPU *_cpu) : TickEvent(_cpu) {} void process(); - const char *description() { return "Timing CPU clock event"; } + const char *description() { return "Timing CPU icache tick"; } }; ITickEvent tickEvent; @@ -155,7 +155,7 @@ class TimingSimpleCPU : public BaseSimpleCPU DTickEvent(TimingSimpleCPU *_cpu) : TickEvent(_cpu) {} void process(); - const char *description() { return "Timing CPU clock event"; } + const char *description() { return "Timing CPU dcache tick"; } }; DTickEvent tickEvent; diff --git a/src/cpu/trace/opt_cpu.cc b/src/cpu/trace/opt_cpu.cc index 996e89f01..0f2944f07 100644 --- a/src/cpu/trace/opt_cpu.cc +++ b/src/cpu/trace/opt_cpu.cc @@ -207,7 +207,7 @@ OptCPU::TickEvent::process() const char * OptCPU::TickEvent::description() { - return "OptCPU tick event"; + return "OptCPU tick"; } diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc index 3c9da4849..32ed6c7d7 100644 --- a/src/cpu/trace/trace_cpu.cc +++ b/src/cpu/trace/trace_cpu.cc @@ -148,7 +148,7 @@ TraceCPU::TickEvent::process() const char * TraceCPU::TickEvent::description() { - return "TraceCPU tick event"; + return "TraceCPU tick"; } diff --git a/src/dev/ethertap.hh b/src/dev/ethertap.hh index f64ed7187..3d2838817 100644 --- a/src/dev/ethertap.hh +++ b/src/dev/ethertap.hh @@ -89,7 +89,7 @@ class EtherTap : public EtherInt TxEvent(EtherTap *_tap) : Event(&mainEventQueue), tap(_tap) {} void process() { tap->retransmit(); } - virtual const char *description() { return "retransmit event"; } + virtual const char *description() { return "EtherTap retransmit"; } }; friend class TxEvent; diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc index 0ad80e077..358dda0d8 100644 --- a/src/dev/uart8250.cc +++ b/src/dev/uart8250.cc @@ -58,7 +58,7 @@ Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit) const char * Uart8250::IntrEvent::description() { - return "uart interrupt delay event"; + return "uart interrupt delay"; } void diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index 7af764437..acae2f126 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -146,7 +146,7 @@ class Bridge : public MemObject virtual void process() { port->trySend(); } - virtual const char *description() { return "bridge send event"; } + virtual const char *description() { return "bridge send"; } }; SendEvent sendEvent; -- cgit v1.2.3