From f1b17bf1576bbc7c5786194cb9a02e3e52dbd1e6 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Wed, 7 Aug 2013 14:51:18 -0500 Subject: ruby: slicc: move some code to AbstractController Some of the code in StateMachine.py file is added to all the controllers and is independent of the controller definition. This code is being moved to the AbstractController class which is the parent class of all controllers. --- src/mem/ruby/slicc_interface/AbstractController.cc | 16 +++++++++++ src/mem/ruby/slicc_interface/AbstractController.hh | 13 +++++---- src/mem/slicc/symbols/StateMachine.py | 33 ---------------------- 3 files changed, 24 insertions(+), 38 deletions(-) diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 930f3a70f..2e4109c01 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -182,3 +182,19 @@ AbstractController::wakeUpAllBuffers() m_waiting_buffers.clear(); } } + +void +AbstractController::blockOnQueue(Address addr, MessageBuffer* port) +{ + m_is_blocking = true; + m_block_map[addr] = port; +} + +void +AbstractController::unblock(Address addr) +{ + m_block_map.erase(addr); + if (m_block_map.size() == 0) { + m_is_blocking = false; + } +} diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 079979bdf..88b82854c 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -56,14 +56,17 @@ class AbstractController : public ClockedObject, public Consumer void init(); const Params *params() const { return (const Params *)_params; } + const int & getVersion() const { return m_version; } + void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } + + // return instance name + const std::string getName() const { return m_name; } + void blockOnQueue(Address, MessageBuffer*); + void unblock(Address); + virtual MessageBuffer* getMandatoryQueue() const = 0; - virtual const int & getVersion() const = 0; virtual const std::string toString() const = 0; // returns text version of // controller type - virtual const std::string getName() const = 0; // return instance name - virtual void blockOnQueue(Address, MessageBuffer*) = 0; - virtual void unblock(Address) = 0; - virtual void initNetworkPtr(Network* net_ptr) = 0; virtual AccessPermission getAccessPermission(const Address& addr) = 0; virtual DataBlock& getDataBlock(const Address& addr) = 0; diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 1eb72972f..6d67f27ba 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -253,10 +253,7 @@ class $c_ident : public AbstractController static int getNumControllers(); void init(); MessageBuffer* getMandatoryQueue() const; - const int & getVersion() const; const std::string toString() const; - const std::string getName() const; - void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } void print(std::ostream& out) const; void wakeup(); @@ -265,8 +262,6 @@ class $c_ident : public AbstractController void regStats(); void collateStats(); - void blockOnQueue(Address addr, MessageBuffer* port); - void unblock(Address addr); void recordCacheTrace(int cntrl, CacheRecorder* tr); Sequencer* getSequencer() const; @@ -840,40 +835,12 @@ $c_ident::getSequencer() const return $seq_ident; } -const int & -$c_ident::getVersion() const -{ - return m_version; -} - const string $c_ident::toString() const { return "$c_ident"; } -const string -$c_ident::getName() const -{ - return m_name; -} - -void -$c_ident::blockOnQueue(Address addr, MessageBuffer* port) -{ - m_is_blocking = true; - m_block_map[addr] = port; -} - -void -$c_ident::unblock(Address addr) -{ - m_block_map.erase(addr); - if (m_block_map.size() == 0) { - m_is_blocking = false; - } -} - void $c_ident::print(ostream& out) const { -- cgit v1.2.3