From f317227b4e5002b2c9d7c2e5068d317dcea5b0f9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 15 May 2007 17:39:50 -0400 Subject: hopefully the final hacky change to make the bus bridge work ok cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here src/mem/bridge.cc: src/mem/bridge.hh: hopefully the final hacky change to make the bus bridge work ok --HG-- extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c --- configs/boot/netperf-stream-udp-client.rcS | 2 +- src/mem/bridge.cc | 44 ++++++++++---------------- src/mem/bridge.hh | 51 +----------------------------- 3 files changed, 18 insertions(+), 79 deletions(-) diff --git a/configs/boot/netperf-stream-udp-client.rcS b/configs/boot/netperf-stream-udp-client.rcS index 91268ea50..4acb4243a 100644 --- a/configs/boot/netperf-stream-udp-client.rcS +++ b/configs/boot/netperf-stream-udp-client.rcS @@ -23,7 +23,7 @@ netcat -c -l -p 8000 BINARY=/benchmarks/netperf-bin/netperf TEST="UDP_STREAM" -SHORT_ARGS="-l 2 -- -m 4096" +SHORT_ARGS="-l 2 -- -m 16384 -M 16384 -s 262144 -S 262144" #LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index f525ccb48..9509aea38 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -247,8 +247,6 @@ Bridge::BridgePort::trySend() { assert(!sendQueue.empty()); - int pbs = peerBlockSize(); - PacketBuffer *buf = sendQueue.front(); assert(buf->ready <= curTick); @@ -257,11 +255,15 @@ Bridge::BridgePort::trySend() pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set + // Ugly! @todo When multilevel coherence works this will be removed if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && - pkt->result != Packet::Nacked && pkt->getOffset(pbs) && - pkt->getSize() != pbs) { - buf->partialWriteFix(this); - pkt = buf->pkt; + pkt->result != Packet::Nacked) { + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr()); + sendFunctional(funcPkt); + pkt->cmd = MemCmd::WriteReq; + delete funcPkt; } DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n", @@ -300,7 +302,6 @@ Bridge::BridgePort::trySend() } } else { DPRINTF(BusBridge, " unsuccessful\n"); - buf->undoPartialWriteFix(); inRetry = true; } DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n", @@ -324,32 +325,18 @@ Bridge::BridgePort::recvRetry() Tick Bridge::BridgePort::recvAtomic(PacketPtr pkt) { - int pbs = otherPort->peerBlockSize(); - Tick atomic_delay; // fix partial atomic writes... similar to the timing code that does the - // same - if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && - pkt->getOffset(pbs) && pkt->getSize() != pbs) { - PacketDataPtr data; - data = new uint8_t[pbs]; - PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq, - Packet::Broadcast, pbs); + // same... will be removed once our code gets this right + if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite) { - funcPkt->dataStatic(data); + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr()); otherPort->sendFunctional(funcPkt); - assert(funcPkt->result == Packet::Success); delete funcPkt; - memcpy(data + pkt->getOffset(pbs), pkt->getPtr(), - pkt->getSize()); - PacketPtr newPkt = new Packet(pkt->req, MemCmd::WriteInvalidateReq, - Packet::Broadcast, pbs); - pkt->dataDynamicArray(data); - atomic_delay = otherPort->sendAtomic(newPkt); - delete newPkt; - } else { - atomic_delay = otherPort->sendAtomic(pkt); + pkt->cmd = MemCmd::WriteReq; } - return atomic_delay + delay; + return delay + otherPort->sendAtomic(pkt); } /** Function called by the port when the bus is receiving a Functional @@ -431,3 +418,4 @@ CREATE_SIM_OBJECT(Bridge) REGISTER_SIM_OBJECT("Bridge", Bridge) + diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index 5951eeb98..a47fe3c1e 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -80,14 +80,10 @@ class Bridge : public MemObject short origSrc; bool expectResponse; - bool partialWriteFixed; - PacketPtr oldPkt; - PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false) : ready(t), pkt(_pkt), origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), - expectResponse(_pkt->needsResponse() && !nack), - partialWriteFixed(false) + expectResponse(_pkt->needsResponse() && !nack) { if (!pkt->isResponse() && !nack && pkt->result != Packet::Nacked) @@ -99,52 +95,7 @@ class Bridge : public MemObject assert(pkt->senderState == this); pkt->setDest(origSrc); pkt->senderState = origSenderState; - if (partialWriteFixed) - delete oldPkt; - } - - void partialWriteFix(Port *port) - { - assert(!partialWriteFixed); - assert(expectResponse); - - Addr pbs = port->peerBlockSize(); - Addr blockAddr = pkt->getAddr() & ~(pbs-1); - partialWriteFixed = true; - PacketDataPtr data; - - data = new uint8_t[pbs]; - RequestPtr funcReq = new Request(blockAddr, 4, 0); - PacketPtr funcPkt = new Packet(funcReq, MemCmd::ReadReq, - Packet::Broadcast); - for (int x = 0; x < pbs; x+=4) { - funcReq->setPhys(blockAddr + x, 4, 0); - funcPkt->reinitFromRequest(); - funcPkt->dataStatic(data + x); - port->sendFunctional(funcPkt); - assert(funcPkt->result == Packet::Success); - } - delete funcPkt; - delete funcReq; - - oldPkt = pkt; - memcpy(data + oldPkt->getOffset(pbs), pkt->getPtr(), - pkt->getSize()); - pkt = new Packet(oldPkt->req, MemCmd::WriteInvalidateReq, - Packet::Broadcast, pbs); - pkt->dataDynamicArray(data); - pkt->senderState = oldPkt->senderState; } - - void undoPartialWriteFix() - { - if (!partialWriteFixed) - return; - delete pkt; - pkt = oldPkt; - partialWriteFixed = false; - } - }; /** -- cgit v1.2.3 From 0934f259d66c7adcf8446e84a2ce7db739794064 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 15 May 2007 18:06:35 -0400 Subject: add an l2 cache option to se example config configs/common/Options.py: configs/example/fs.py: move l2 cache option to Options.py --HG-- extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8 --- configs/common/Options.py | 3 ++- configs/example/fs.py | 1 - configs/example/se.py | 11 +++++++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/configs/common/Options.py b/configs/common/Options.py index 69f48dc3b..4f2b317c0 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,6 +31,7 @@ parser.add_option("-d", "--detailed", action="store_true") parser.add_option("-t", "--timing", action="store_true") parser.add_option("-n", "--num_cpus", type="int", default=1) parser.add_option("--caches", action="store_true") +parser.add_option("--l2cache", action="store_true") # Run duration options parser.add_option("-m", "--maxtick", type="int") diff --git a/configs/example/fs.py b/configs/example/fs.py index bd4637e95..76c12bd9e 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -51,7 +51,6 @@ parser.add_option("--kernel", action="store", type="string") parser.add_option("--script", action="store", type="string") # Benchmark options -parser.add_option("--l2cache", action="store_true") parser.add_option("--dual", action="store_true", help="Simulate two systems attached with an ethernet link") parser.add_option("-b", "--benchmark", action="store", type="string", diff --git a/configs/example/se.py b/configs/example/se.py index 0944a030e..b294480f6 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -104,7 +104,14 @@ for i in xrange(np): if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) - system.cpu[i].connectMemPorts(system.membus) + if options.l2cache: + system.l2 = L2Cache(size='2MB') + system.tol2bus = Bus() + system.l2.cpu_side = system.tol2bus.port + system.l2.mem_side = system.membus.port + system.cpu[i].connectMemPorts(system.tol2bus) + else: + system.cpu[i].connectMemPorts(system.membus) system.cpu[i].workload = process root = Root(system = system) -- cgit v1.2.3