From f5c7b1358cf0b27c27c10eae42e09949613e24a9 Mon Sep 17 00:00:00 2001 From: Andrew Schultz Date: Wed, 19 May 2004 15:58:24 -0400 Subject: Remove the uncacheable bit 39 check (needs to be merged in with head tree if Tru64 is to continue to be supported on Turbolaser) and fixed translation of physical addresses by clearing PA<42:35> when the real uncachable bit (43) is set arch/alpha/ev5.hh: Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6 also add support proper translation of uncacheable physical addresses dev/ide_ctrl.cc: Fix to work with real address translation --HG-- extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a --- arch/alpha/alpha_memory.cc | 51 +++++++++++++++------------------------------- arch/alpha/ev5.hh | 13 +++++++----- dev/ide_ctrl.cc | 10 ++++----- 3 files changed, 29 insertions(+), 45 deletions(-) diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 0c1be519d..1a1c738ec 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -101,25 +101,7 @@ AlphaTLB::checkCacheability(MemReqPtr &req) * to catch a weird case where both are used, which shouldn't happen. */ - if (req->paddr & PA_UNCACHED_BIT_40 || - req->paddr & PA_UNCACHED_BIT_39) { - -#ifdef DEBUG - if (req->paddr & PA_UNCACHED_BIT_40) { - if(uncacheBit39) - panic("Bit 40 access follows bit 39 access, PA=%x\n", - req->paddr); - - uncacheBit40 = true; - } else if (req->paddr & PA_UNCACHED_BIT_39) { - if(uncacheBit40) - panic("Bit 39 acceess follows bit 40 access, PA=%x\n", - req->paddr); - - uncacheBit39 = true; - } -#endif - + if (req->paddr & PA_UNCACHED_BIT_43) { // IPR memory space not implemented if (PA_IPR_SPACE(req->paddr)) if (!req->xc->misspeculating()) @@ -128,6 +110,9 @@ AlphaTLB::checkCacheability(MemReqPtr &req) // mark request as uncacheable req->flags |= UNCACHEABLE; + + // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) + req->paddr &= PA_UNCACHED_MASK; } } @@ -313,10 +298,10 @@ AlphaITB::translate(MemReqPtr &req) const return ITB_Acv_Fault; } - // Check for "superpage" mapping: when SP<1> is set, and - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. - if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE(req->vaddr) == 2) { + + // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 + // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 + if (VA_SPACE_EV6(req->vaddr) == 0x7e) { // only valid in kernel mode if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) { @@ -328,11 +313,10 @@ AlphaITB::translate(MemReqPtr &req) const req->paddr = req->vaddr & PA_IMPL_MASK; // sign extend the physical address properly - if (req->paddr & PA_UNCACHED_BIT_39 || - req->paddr & PA_UNCACHED_BIT_40) - req->paddr |= 0xf0000000000ULL; + if (req->paddr & PA_UNCACHED_BIT_40) + req->paddr |= ULL(0xf0000000000); else - req->paddr &= 0xffffffffffULL; + req->paddr &= ULL(0xffffffffff); } else { // not a physical address: need to look up pte @@ -499,10 +483,8 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const return DTB_Fault_Fault; } - // Check for "superpage" mapping: when SP<1> is set, and - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. - if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE(req->vaddr) == 2) { + // Check for "superpage" mapping + if (VA_SPACE_EV6(req->vaddr) == 0x7e) { // only valid in kernel mode if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != @@ -517,11 +499,10 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const req->paddr = req->vaddr & PA_IMPL_MASK; // sign extend the physical address properly - if (req->paddr & PA_UNCACHED_BIT_39 || - req->paddr & PA_UNCACHED_BIT_40) - req->paddr |= 0xf0000000000ULL; + if (req->paddr & PA_UNCACHED_BIT_40) + req->paddr |= ULL(0xf0000000000); else - req->paddr &= 0xffffffffffULL; + req->paddr &= ULL(0xffffffffff); } else { if (write) diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh index bd4115704..636e37adb 100644 --- a/arch/alpha/ev5.hh +++ b/arch/alpha/ev5.hh @@ -32,8 +32,8 @@ #define ALT_MODE_AM(X) (((X) >> 3) & 0x3) #define DTB_CM_CM(X) (((X) >> 3) & 0x3) -#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f) -#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff) +#define DTB_ASN_ASN(X) (((X) >> 57) & 0xff) +#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff) #define DTB_PTE_XRE(X) (((X) >> 8) & 0xf) #define DTB_PTE_XWE(X) (((X) >> 12) & 0xf) #define DTB_PTE_FONR(X) (((X) >> 1) & 0x1) @@ -42,8 +42,8 @@ #define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1) #define ICM_CM(X) (((X) >> 3) & 0x3) -#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f) -#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff) +#define ITB_ASN_ASN(X) (((X) >> 4) & 0xff) +#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff) #define ITB_PTE_XRE(X) (((X) >> 8) & 0xf) #define ITB_PTE_FONR(X) (((X) >> 1) & 0x1) #define ITB_PTE_FONW(X) (((X) >> 2) & 0x1) @@ -54,12 +54,15 @@ #define VA_IMPL_MASK ULL(0x000007ffffffffff) #define VA_IMPL(X) ((X) & VA_IMPL_MASK) #define VA_VPN(X) (VA_IMPL(X) >> 13) -#define VA_SPACE(X) (((X) >> 41) & 0x3) +#define VA_SPACE_EV5(X) (((X) >> 41) & 0x3) +#define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f) #define VA_POFS(X) ((X) & 0x1fff) #define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami #define PA_UNCACHED_BIT_39 ULL(0x8000000000) #define PA_UNCACHED_BIT_40 ULL(0x10000000000) +#define PA_UNCACHED_BIT_43 ULL(0x80000000000) +#define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35> #define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000)) #define PA_PFN2PA(X) ((X) << 13) diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index a21cf12d7..f78a8e1ef 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -357,7 +357,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(pri_cmd_addr, pri_cmd_addr + pri_cmd_size - 1); - pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + pri_cmd_addr = pri_cmd_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR1: @@ -366,7 +366,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(pri_ctrl_addr, pri_ctrl_addr + pri_ctrl_size - 1); - pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + pri_ctrl_addr = pri_ctrl_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR2: @@ -375,7 +375,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(sec_cmd_addr, sec_cmd_addr + sec_cmd_size - 1); - sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + sec_cmd_addr = sec_cmd_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR3: @@ -384,7 +384,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(sec_ctrl_addr, sec_ctrl_addr + sec_ctrl_size - 1); - sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + sec_ctrl_addr = sec_ctrl_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR4: @@ -392,7 +392,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) if (pioInterface) pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1); - bmi_addr = ((bmi_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + bmi_addr = bmi_addr & PA_UNCACHED_MASK; break; } } -- cgit v1.2.3