From f7a75d872b4bf94aafcfcb5f773afda75f7c3499 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 3 Feb 2006 03:38:27 -0500 Subject: Checkin (Merge?) files ... Added a few new format files arch/mips/isa/formats/fpop.format: Floating Point Formats arch/mips/isa/formats/tlb.format: TLB Ops Format arch/mips/isa/mips.isa: Name change to mips.isa --HG-- rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h extra : convert_revision : 069a24da405b613f688e693fd038ac7a30a4faed --- arch/mips/isa/bitfields.h | 51 +++ arch/mips/isa/decoder.h | 575 ++++++++++++++++++++++++++++ arch/mips/isa/formats.h | 22 ++ arch/mips/isa/formats/basic.format | 65 ++++ arch/mips/isa/formats/branch.format | 66 ++++ arch/mips/isa/formats/fpop.format | 110 ++++++ arch/mips/isa/formats/integerop.format | 110 ++++++ arch/mips/isa/formats/mem.format | 78 ++++ arch/mips/isa/formats/noop.format | 47 +++ arch/mips/isa/formats/tlb.format | 53 +++ arch/mips/isa/formats/trap.format | 53 +++ arch/mips/isa/includes.h | 40 ++ arch/mips/isa/mips.isa | 52 +++ arch/mips/isa/operands.h | 33 ++ arch/mips/isa_desc/bitfields.h | 51 --- arch/mips/isa_desc/decoder.h | 575 ---------------------------- arch/mips/isa_desc/formats.h | 22 -- arch/mips/isa_desc/formats/basic.format | 65 ---- arch/mips/isa_desc/formats/branch.format | 66 ---- arch/mips/isa_desc/formats/integerop.format | 110 ------ arch/mips/isa_desc/formats/mem.format | 78 ---- arch/mips/isa_desc/formats/noop.format | 47 --- arch/mips/isa_desc/formats/trap.format | 53 --- arch/mips/isa_desc/includes.h | 40 -- arch/mips/isa_desc/operands.h | 33 -- 25 files changed, 1355 insertions(+), 1140 deletions(-) create mode 100644 arch/mips/isa/bitfields.h create mode 100644 arch/mips/isa/decoder.h create mode 100644 arch/mips/isa/formats.h create mode 100644 arch/mips/isa/formats/basic.format create mode 100644 arch/mips/isa/formats/branch.format create mode 100644 arch/mips/isa/formats/fpop.format create mode 100644 arch/mips/isa/formats/integerop.format create mode 100644 arch/mips/isa/formats/mem.format create mode 100644 arch/mips/isa/formats/noop.format create mode 100644 arch/mips/isa/formats/tlb.format create mode 100644 arch/mips/isa/formats/trap.format create mode 100644 arch/mips/isa/includes.h create mode 100644 arch/mips/isa/mips.isa create mode 100644 arch/mips/isa/operands.h delete mode 100644 arch/mips/isa_desc/bitfields.h delete mode 100644 arch/mips/isa_desc/decoder.h delete mode 100644 arch/mips/isa_desc/formats.h delete mode 100644 arch/mips/isa_desc/formats/basic.format delete mode 100644 arch/mips/isa_desc/formats/branch.format delete mode 100644 arch/mips/isa_desc/formats/integerop.format delete mode 100644 arch/mips/isa_desc/formats/mem.format delete mode 100644 arch/mips/isa_desc/formats/noop.format delete mode 100644 arch/mips/isa_desc/formats/trap.format delete mode 100644 arch/mips/isa_desc/includes.h delete mode 100644 arch/mips/isa_desc/operands.h diff --git a/arch/mips/isa/bitfields.h b/arch/mips/isa/bitfields.h new file mode 100644 index 000000000..f0d6fc8d7 --- /dev/null +++ b/arch/mips/isa/bitfields.h @@ -0,0 +1,51 @@ +//////////////////////////////////////////////////////////////////// +// +// Bitfield definitions. +// + +def bitfield OPCODE_HI <31:29>; +def bitfield OPCODE_LO <28:26>; + +def bitfield FUNCTION_HI < 5: 3>; +def bitfield FUNCTION_LO < 2: 0>; + +def bitfield RT <20:16>; +def bitfield RT_HI <20:19>; +def bitfield RT_LO <18:16>; + +def bitfield RS <25:21>; +def bitfield RS_HI <25:24>; +def bitfield RS_LO <23:21>; + +def bitfield RD <15:11>; + +// Floating-point operate format +def bitfield FMT <25:21>; +def bitfield FT <20:16>; +def bitfield FS <15:11>; +def bitfield FD <10:6>; + +def bitfield MOVCI <16:16>; +def bitfield MOVCF <16:16>; +def bitfield SRL <21:21>; +def bitfield SRLV < 6: 6>; +def bitfield SA <10: 6>; + +// Interrupts +def bitfield SC < 5: 5>; + +// Integer operate format(s>; +def bitfield INTIMM <15: 0>; // integer immediate (literal) + +// Branch format +def bitfield OFFSET <15: 0>; // displacement + +// Memory-format jumps +def bitfield JMPTARG <25: 0>; +def bitfield JMPHINT <10: 6>; + +def bitfield SYSCALLCODE <25: 6>; +def bitfield TRAPCODE <15:13>; + +// M5 instructions +def bitfield M5FUNC <7:0>; diff --git a/arch/mips/isa/decoder.h b/arch/mips/isa/decoder.h new file mode 100644 index 000000000..7e911cb45 --- /dev/null +++ b/arch/mips/isa/decoder.h @@ -0,0 +1,575 @@ +//////////////////////////////////////////////////////////////////// +// +// The actual MIPS32 ISA decoder +// ----------------------------- +// The following instructions are specified in the MIPS32 ISA +// Specification. Decoding closely follows the style specified +// in the MIPS32 ISAthe specification document starting with Table +// A-2 (document available @ www.mips.com) +// +//@todo: Distinguish "unknown/future" use insts from "reserved" +// ones +decode OPCODE_HI default FailUnimpl::unknown() { + + // Derived From ... Table A-2 MIPS32 ISA Manual + 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ + + 0x0: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x1: decode MOVCI { + format Move { + 0: movc({{ }}); + 1: movt({{ }}); + } + } + + format ShiftRotate { + //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields + //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." + 0x0: sll({{ }}); + + 0x2: decode SRL { + 0: srl({{ }}); + 1: rotr({{ }}); + } + + 0x3: sar({{ }}); + + 0x4: sllv({{ }}); + + 0x6: decode SRLV { + 0: srlv({{ }}); + 1: rotrv({{ }}); + } + + 0x7: srav({{ }}); + } + } + + 0x1: decode FUNCTION_LO { + + //Table A-3 Note: "Specific encodings of the hint field are used + //to distinguish JR from JR.HB and JALR from JALR.HB" + format Jump { + 0x0: jr({{ }}); + 0x1: jalr({{ }}); + } + + format Move { + 0x2: movz({{ }}); + 0x3: movn({{ }}); + } + + 0x4: Syscall::syscall({{ }}); + 0x5: Break::break({{ }}); + 0x7: Synchronize::synch({{ }}); + } + + 0x2: decode FUNCTION_LO { + format MultDiv { + 0x0: mfhi({{ }}); + 0x1: mthi({{ }}); + 0x2: mflo({{ }}); + 0x3: mtlo({{ }}); + } + }; + + 0x3: decode FUNCTION_LO { + format MultDiv { + 0x0: mult({{ }}); + 0x1: multu({{ }}); + 0x2: div({{ }}); + 0x3: divu({{ }}); + } + }; + + 0x4: decode FUNCTION_LO { + format Arithmetic { + 0x0: add({{ }}); + 0x1: addu({{ }}); + 0x2: sub({{ }}); + 0x3: subu({{ }}); + } + + format Logical { + 0x0: and({{ }}); + 0x1: or({{ }}); + 0x2: xor({{ }}); + 0x3: nor({{ }}); + } + } + + 0x5: decode FUNCTION_LO { + format SetInstructions{ + 0x2: slt({{ }}); + 0x3: sltu({{ }}); + } + }; + + 0x6: decode FUNCTION_LO { + format Trap { + 0x0: tge({{ }}); + 0x1: tgeu({{ }}); + 0x2: tlt({{ }}); + 0x3: tltu({{ }}); + 0x4: teq({{ }}); + 0x6: tne({{ }}); + } + } + } + + 0x1: decode REGIMM_HI { + 0x0: decode REGIMM_LO { + format Branch { + 0x0: bltz({{ }}); + 0x1: bgez({{ }}); + + //MIPS obsolete instructions + 0x2: bltzl({{ }}); + 0x3: bgezl({{ }}); + } + } + + 0x1: decode REGIMM_LO { + format Trap { + 0x0: tgei({{ }}); + 0x1: tgeiu({{ }}); + 0x2: tlti({{ }}); + 0x3: tltiu({{ }}); + 0x4: teqi({{ }}); + 0x6: tnei({{ }}); + } + } + + 0x2: decode REGIMM_LO { + format Branch { + 0x0: bltzal({{ }}); + 0x1: bgezal({{ }}); + + //MIPS obsolete instructions + 0x2: bltzall({{ }}); + 0x3: bgezall({{ }}); + } + } + + 0x3: decode REGIMM_LO { + 0x7: synci({{ }}); + } + } + + format Jump { + 0x2: j({{ }}); + 0x3: jal({{ }}); + } + + format Branch { + 0x4: beq({{ }}); + 0x5: bne({{ }}); + 0x6: blez({{ }}); + 0x7: bgtz({{ }}); + } + }; + + 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ + format IntImmediate { + 0x0: addi({{ }}); + 0x1: addiu({{ }}); + 0x2: slti({{ }}); + 0x3: sltiu({{ }}); + 0x4: andi({{ }}); + 0x5: ori({{ }}); + 0x6: xori({{ }}); + 0x7: lui({{ }}); + }; + }; + + 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ + + //Table A-11 MIPS32 COP0 Encoding of rs Field + 0x0: decode RS_MSB { + 0x0: decode RS { + 0x0: mfc0({{ }}); + 0xC: mtc0({{ }}); + 0xA: rdpgpr({{ }}); + + 0xB: decode SC { + 0x0: di({{ }}); + 0x1: ei({{ }}); + } + + 0xE: wrpgpr({{ }}); + } + + //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO + 0x1: decode FUNCTION { + 0x01: tlbr({{ }}); + 0x02: tlbwi({{ }}); + 0x06: tlbwr({{ }}); + 0x08: tlbp({{ }}); + 0x18: eret({{ }}); + 0x1F: deret({{ }}); + 0x20: wait({{ }}); + } + } + + //Table A-13 MIPS32 COP1 Encoding of rs Field + 0x1: decode RS_MSB { + + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc1({{ }}); + 0x2: cfc1({{ }}); + 0x3: mfhc1({{ }}); + 0x4: mtc1({{ }}); + 0x6: ctc1({{ }}); + 0x7: mftc1({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + 0x0: bc1f({{ }}); + 0x1: bc1t({{ }}); + } + + 0x1: decode TF { + 0x0: bc1fl({{ }}); + 0x1: bc1tl({{ }}); + } + } + } + + 0x1: decode RS_HI { + 0x2: decode RS_LO { + + //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S + //(( single-word )) + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + + format mode64 { + 0x2: recip({{ }}); + 0x3: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x1: cvt_d({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + 0x6: cvt_ps({{ }}); + } + } + } + + //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D + 0x1: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + + format mode64 { + 0x5: recip({{ }}); + 0x6: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x0: cvt_s({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + } + } + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W + 0x4: decode FUNCTION { + 0x10: cvt_s({{ }}); + 0x10: cvt_d({{ }}); + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 + //Note: "1. Format type L is legal only if 64-bit floating point operations + //are enabled." + 0x5: decode FUNCTION_HI { + 0x10: cvt_s({{ }}); + 0x11: cvt_d({{ }}); + } + + //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 + //Note: "1. Format type PS is legal only if 64-bit floating point operations + //are enabled. " + 0x6: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + } + + 0x4: decode RS_LO { + 0x0: cvt_s_pu({{ }}); + } + + 0x5: decode RS_LO { + 0x0: cvt_s_pl({{ }}); + 0x4: pll_s_pl({{ }}); + 0x5: plu_s_pl({{ }}); + 0x6: pul_s_pl({{ }}); + 0x7: puu_s_pl({{ }}); + } + } + } + + //Table A-19 MIPS32 COP2 Encoding of rs Field + 0x2: decode RS_MSB { + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc2({{ }}); + 0x2: cfc2({{ }}); + 0x3: mfhc2({{ }}); + 0x4: mtc2({{ }}); + 0x6: ctc2({{ }}); + 0x7: mftc2({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + 0x0: bc2f({{ }}); + 0x1: bc2t({{ }}); + } + + 0x1: decode TF { + 0x0: bc2fl({{ }}); + 0x1: bc2tl({{ }}); + } + } + } + } + + //Table A-20 MIPS64 COP1X Encoding of Function Field 1 + //Note: "COP1X instructions are legal only if 64-bit floating point + //operations are enabled." + 0x3: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x0: lwxc1({{ }}); + 0x1: ldxc1({{ }}); + 0x5: luxc1({{ }}); + } + + 0x1: decode FUNCTION_LO { + 0x0: swxc1({{ }}); + 0x1: sdxc1({{ }}); + 0x5: suxc1({{ }}); + 0x7: prefx({{ }}); + } + + 0x3: alnv_ps({{ }}); + + 0x4: decode FUNCTION_LO { + 0x0: madd_s({{ }}); + 0x1: madd_d({{ }}); + 0x6: madd_ps({{ }}); + } + + 0x5: decode FUNCTION_LO { + 0x0: msub_s({{ }}); + 0x1: msub_d({{ }}); + 0x6: msub_ps({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x0: nmadd_s({{ }}); + 0x1: nmadd_d({{ }}); + 0x6: nmadd_ps({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x0: nmsub_s({{ }}); + 0x1: nmsub_d({{ }}); + 0x6: nmsub_ps({{ }}); + } + } + + //MIPS obsolete instructions + 0x4: beql({{ }}); + 0x5: bnel({{ }}); + 0x6: blezl({{ }}); + 0x7: bgtzl({{ }}); + }; + + 0x3: decode OPCODE_LO default FailUnimpl::reserved(){ + + //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field + 0x4: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + 0x0: madd({{ }}); + 0x1: maddu({{ }}); + 0x2: mult({{ }}); + 0x4: msub({{ }}); + 0x5: msubu({{ }}); + } + + 0x4: decode FUNCTION_LO { + 0x0: clz({{ }}); + 0x1: clo({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x7: sdbbp({{ }}); + } + } + + //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture + 0x7: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + 0x1: ext({{ }}); + 0x4: ins({{ }}); + } + + //Table A-10 MIPS32 BSHFL Encoding of sa Field + 0x4: decode SA { + 0x02: wsbh({{ }}); + 0x10: seb({{ }}); + 0x18: seh({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x7: rdhwr({{ }}); + } + } + }; + + 0x4: decode OPCODE_LO default FailUnimpl::reserved(){ + format LoadMemory{ + 0x0: lb({{ }}); + 0x1: lh({{ }}); + 0x2: lwl({{ }}); + 0x3: lw({{ }}); + 0x4: lbu({{ }}); + 0x5: lhu({{ }}); + 0x6: lhu({{ }}); + }; + + 0x7: FailUnimpl::reserved({{ }}); + }; + + 0x5: decode OPCODE_LO default FailUnimpl::reserved(){ + format StoreMemory{ + 0x0: sb({{ }}); + 0x1: sh({{ }}); + 0x2: swl({{ }}); + 0x3: sw({{ }}); + 0x6: swr({{ }}); + }; + + format FailUnimpl{ + 0x4: reserved({{ }}); + 0x5: reserved({{ }}); + 0x7: cache({{ }}); + }; + + }; + + 0x6: decode OPCODE_LO default FailUnimpl::reserved(){ + format LoadMemory{ + 0x0: ll({{ }}); + 0x1: lwc1({{ }}); + 0x5: ldc1({{ }}); + }; + }; + + 0x7: decode OPCODE_LO default FailUnimpl::reserved(){ + format StoreMemory{ + 0x0: sc({{ }}); + 0x1: swc1({{ }}); + 0x5: sdc1({{ }}); + }; + + } +} + + diff --git a/arch/mips/isa/formats.h b/arch/mips/isa/formats.h new file mode 100644 index 000000000..404314c7a --- /dev/null +++ b/arch/mips/isa/formats.h @@ -0,0 +1,22 @@ +//Include the basic format +//Templates from this format are used later +##include "m5/arch/mips/isa_desc/formats/basic.format" + +//Include the integerOp and integerOpCc format +##include "m5/arch/mips/isa_desc/formats/integerop.format" + +//Include the floatOp format +##include "m5/arch/mips/isa_desc/formats/floatop.format" + +//Include the mem format +##include "m5/arch/mips/isa_desc/formats/mem.format" + +//Include the trap format +##include "m5/arch/mips/isa_desc/formats/trap.format" + +//Include the branch format +##include "m5/arch/mips/isa_desc/formats/branch.format" + +//Include the noop format +##include "m5/arch/mips/isa_desc/formats/noop.format" + diff --git a/arch/mips/isa/formats/basic.format b/arch/mips/isa/formats/basic.format new file mode 100644 index 000000000..8fba9845a --- /dev/null +++ b/arch/mips/isa/formats/basic.format @@ -0,0 +1,65 @@ + +// Declarations for execute() methods. +def template BasicExecDeclare {{ + Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +// Basic instruction class declaration template. +def template BasicDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + /// Constructor. + %(class_name)s(MachInst machInst); + %(BasicExecDeclare)s + }; +}}; + +// Basic instruction class constructor template. +def template BasicConstructor {{ + inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + { + %(constructor)s; + } +}}; + +// Basic instruction class execute method template. +def template BasicExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if(fault == No_Fault) + { + %(op_wb)s; + } + return fault; + } +}}; + +// Basic decode template. +def template BasicDecode {{ + return new %(class_name)s(machInst); +}}; + +// Basic decode template, passing mnemonic in as string arg to constructor. +def template BasicDecodeWithMnemonic {{ + return new %(class_name)s("%(mnemonic)s", machInst); +}}; + +// The most basic instruction format... used only for a few misc. insts +def format BasicOperate(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/branch.format b/arch/mips/isa/formats/branch.format new file mode 100644 index 000000000..5327f30e8 --- /dev/null +++ b/arch/mips/isa/formats/branch.format @@ -0,0 +1,66 @@ +//////////////////////////////////////////////////////////////////// +// +// Branch instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Branch : public MipsStaticInst + { + protected: + + /// Constructor + Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template BranchExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Branch(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = BranchExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/fpop.format b/arch/mips/isa/formats/fpop.format new file mode 100644 index 000000000..a058eea19 --- /dev/null +++ b/arch/mips/isa/formats/fpop.format @@ -0,0 +1,110 @@ +//////////////////////////////////////////////////////////////////// +// +// Floating Point operate instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class FPOp : public MipsStaticInst + { + protected: + + /// Constructor + FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template IntegerExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //These are set to constants when the execute method + //is generated + bool useCc = ; + bool checkPriv = ; + + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + if(useCc) + { + xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); + xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); + xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; + xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; + xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); + xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); + xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; + xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; + } + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format FPOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', '0'), ('icValue', '0'), + ('xvValue', '0'), ('xcValue', '0')): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; + +// Primary format for integer operate instructions: +def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), + ('xvValue', xvValue), ('xcValue', xcValue)): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/integerop.format b/arch/mips/isa/formats/integerop.format new file mode 100644 index 000000000..6fa7feed3 --- /dev/null +++ b/arch/mips/isa/formats/integerop.format @@ -0,0 +1,110 @@ +//////////////////////////////////////////////////////////////////// +// +// Integer operate instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class IntegerOp : public MipsStaticInst + { + protected: + + /// Constructor + IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template IntegerExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //These are set to constants when the execute method + //is generated + bool useCc = ; + bool checkPriv = ; + + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + if(useCc) + { + xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); + xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); + xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; + xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; + xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); + xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); + xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; + xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; + } + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format IntegerOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', '0'), ('icValue', '0'), + ('xvValue', '0'), ('xcValue', '0')): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; + +// Primary format for integer operate instructions: +def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), + ('xvValue', xvValue), ('xcValue', xcValue)): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/mem.format b/arch/mips/isa/formats/mem.format new file mode 100644 index 000000000..5ed5237c5 --- /dev/null +++ b/arch/mips/isa/formats/mem.format @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////////////////// +// +// Mem instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Mem : public MipsStaticInst + { + protected: + + /// Constructor + Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template MemExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + + %(op_decl)s; + %(op_rd)s; + ea_code + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Mem(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); +}}; + +def format Cas(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = R1;'); +}}; diff --git a/arch/mips/isa/formats/noop.format b/arch/mips/isa/formats/noop.format new file mode 100644 index 000000000..b1ece654d --- /dev/null +++ b/arch/mips/isa/formats/noop.format @@ -0,0 +1,47 @@ +//////////////////////////////////////////////////////////////////// +// +// Noop instruction +// + +output header {{ + /** + * Base class for integer operations. + */ + class Noop : public MipsStaticInst + { + protected: + + /// Constructor + Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template NoopExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Nothing to see here, move along + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Noop(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = NoopExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/tlb.format b/arch/mips/isa/formats/tlb.format new file mode 100644 index 000000000..f5e4076f2 --- /dev/null +++ b/arch/mips/isa/formats/tlb.format @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////// +// +// TlbOp instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class TlbOp : public MipsStaticInst + { + protected: + + /// Constructor + TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template TlbOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Call into the trap handler with the appropriate fault + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format TlbOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TlbOpExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/trap.format b/arch/mips/isa/formats/trap.format new file mode 100644 index 000000000..78f8d87b0 --- /dev/null +++ b/arch/mips/isa/formats/trap.format @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////// +// +// Trap instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Trap : public MipsStaticInst + { + protected: + + /// Constructor + Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template TrapExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Call into the trap handler with the appropriate fault + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Trap(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TrapExecute.subst(iop) +}}; diff --git a/arch/mips/isa/includes.h b/arch/mips/isa/includes.h new file mode 100644 index 000000000..ff7cb7d1d --- /dev/null +++ b/arch/mips/isa/includes.h @@ -0,0 +1,40 @@ +//////////////////////////////////////////////////////////////////// +// +// Output include file directives. +// + +output header {{ +#include +#include +#include + +#include "cpu/static_inst.hh" +#include "traps.hh" +#include "mem/mem_req.hh" // some constructors use MemReq flags +}}; + +output decoder {{ +#include "base/cprintf.hh" +#include "base/loader/symtab.hh" +#include "cpu/exec_context.hh" // for Jump::branchTarget() + +#include +#if defined(linux) +#include +#endif +}}; + +output exec {{ +#include +#if defined(linux) +#include +#endif + +#ifdef FULL_SYSTEM +//#include "arch/alpha/pseudo_inst.hh" +#endif +#include "cpu/base.hh" +#include "cpu/exetrace.hh" +#include "sim/sim_exit.hh" +}}; + diff --git a/arch/mips/isa/mips.isa b/arch/mips/isa/mips.isa new file mode 100644 index 000000000..a8c71872b --- /dev/null +++ b/arch/mips/isa/mips.isa @@ -0,0 +1,52 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2003-2005 The Regents of The University of Michigan +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +##include "m5/arch/sparc/isa_desc/includes.h" + +//////////////////////////////////////////////////////////////////// +// +// Namespace statement. Everything below this line will be in the +// MipsISAInst namespace. +// + +namespace MipsISA; + +//Include the bitfield definitions +##include "m5/arch/mips/isa_desc/bitfields.h" + +//Include the operand_types and operand definitions +##include "m5/arch/mips/isa_desc/operands.h" + +//Include the base class for mips instructions, and some support code +##include "m5/arch/mips/isa_desc/base.h" + +//Include the definitions for the instruction formats +##include "m5/arch/mips/isa_desc/formats.h" + +//Include the decoder definition +##include "m5/arch/mips/isa_desc/decoder.h" diff --git a/arch/mips/isa/operands.h b/arch/mips/isa/operands.h new file mode 100644 index 000000000..77de6c9c4 --- /dev/null +++ b/arch/mips/isa/operands.h @@ -0,0 +1,33 @@ +def operand_types {{ + 'sb' : ('signed int', 8), + 'ub' : ('unsigned int', 8), + 'shw' : ('signed int', 16), + 'uhw' : ('unsigned int', 16), + 'sw' : ('signed int', 32), + 'uw' : ('unsigned int', 32), + 'sdw' : ('signed int', 64), + 'udw' : ('unsigned int', 64), + 'sf' : ('float', 32), + 'df' : ('float', 64), + 'qf' : ('float', 128) +}}; + +def operands {{ + # Int regs default to unsigned, but code should not count on this. + # For clarity, descriptions that depend on unsigned behavior should + # explicitly specify '.uq'. + 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1), + 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2), + 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3), + #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), + #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), + #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), + 'Mem': MemOperandTraits('udw', None, + ('IsMemRef', 'IsLoad', 'IsStore'), 4) + #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), + #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), + #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), + # The next two are hacks for non-full-system call-pal emulation + #'R0': IntRegOperandTraits('uq', '0', None, 1), + #'R16': IntRegOperandTraits('uq', '16', None, 1) +}}; diff --git a/arch/mips/isa_desc/bitfields.h b/arch/mips/isa_desc/bitfields.h deleted file mode 100644 index f0d6fc8d7..000000000 --- a/arch/mips/isa_desc/bitfields.h +++ /dev/null @@ -1,51 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Bitfield definitions. -// - -def bitfield OPCODE_HI <31:29>; -def bitfield OPCODE_LO <28:26>; - -def bitfield FUNCTION_HI < 5: 3>; -def bitfield FUNCTION_LO < 2: 0>; - -def bitfield RT <20:16>; -def bitfield RT_HI <20:19>; -def bitfield RT_LO <18:16>; - -def bitfield RS <25:21>; -def bitfield RS_HI <25:24>; -def bitfield RS_LO <23:21>; - -def bitfield RD <15:11>; - -// Floating-point operate format -def bitfield FMT <25:21>; -def bitfield FT <20:16>; -def bitfield FS <15:11>; -def bitfield FD <10:6>; - -def bitfield MOVCI <16:16>; -def bitfield MOVCF <16:16>; -def bitfield SRL <21:21>; -def bitfield SRLV < 6: 6>; -def bitfield SA <10: 6>; - -// Interrupts -def bitfield SC < 5: 5>; - -// Integer operate format(s>; -def bitfield INTIMM <15: 0>; // integer immediate (literal) - -// Branch format -def bitfield OFFSET <15: 0>; // displacement - -// Memory-format jumps -def bitfield JMPTARG <25: 0>; -def bitfield JMPHINT <10: 6>; - -def bitfield SYSCALLCODE <25: 6>; -def bitfield TRAPCODE <15:13>; - -// M5 instructions -def bitfield M5FUNC <7:0>; diff --git a/arch/mips/isa_desc/decoder.h b/arch/mips/isa_desc/decoder.h deleted file mode 100644 index 7e911cb45..000000000 --- a/arch/mips/isa_desc/decoder.h +++ /dev/null @@ -1,575 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// The actual MIPS32 ISA decoder -// ----------------------------- -// The following instructions are specified in the MIPS32 ISA -// Specification. Decoding closely follows the style specified -// in the MIPS32 ISAthe specification document starting with Table -// A-2 (document available @ www.mips.com) -// -//@todo: Distinguish "unknown/future" use insts from "reserved" -// ones -decode OPCODE_HI default FailUnimpl::unknown() { - - // Derived From ... Table A-2 MIPS32 ISA Manual - 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ - - 0x0: decode FUNCTION_HI { - 0x0: decode FUNCTION_LO { - 0x1: decode MOVCI { - format Move { - 0: movc({{ }}); - 1: movt({{ }}); - } - } - - format ShiftRotate { - //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields - //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." - 0x0: sll({{ }}); - - 0x2: decode SRL { - 0: srl({{ }}); - 1: rotr({{ }}); - } - - 0x3: sar({{ }}); - - 0x4: sllv({{ }}); - - 0x6: decode SRLV { - 0: srlv({{ }}); - 1: rotrv({{ }}); - } - - 0x7: srav({{ }}); - } - } - - 0x1: decode FUNCTION_LO { - - //Table A-3 Note: "Specific encodings of the hint field are used - //to distinguish JR from JR.HB and JALR from JALR.HB" - format Jump { - 0x0: jr({{ }}); - 0x1: jalr({{ }}); - } - - format Move { - 0x2: movz({{ }}); - 0x3: movn({{ }}); - } - - 0x4: Syscall::syscall({{ }}); - 0x5: Break::break({{ }}); - 0x7: Synchronize::synch({{ }}); - } - - 0x2: decode FUNCTION_LO { - format MultDiv { - 0x0: mfhi({{ }}); - 0x1: mthi({{ }}); - 0x2: mflo({{ }}); - 0x3: mtlo({{ }}); - } - }; - - 0x3: decode FUNCTION_LO { - format MultDiv { - 0x0: mult({{ }}); - 0x1: multu({{ }}); - 0x2: div({{ }}); - 0x3: divu({{ }}); - } - }; - - 0x4: decode FUNCTION_LO { - format Arithmetic { - 0x0: add({{ }}); - 0x1: addu({{ }}); - 0x2: sub({{ }}); - 0x3: subu({{ }}); - } - - format Logical { - 0x0: and({{ }}); - 0x1: or({{ }}); - 0x2: xor({{ }}); - 0x3: nor({{ }}); - } - } - - 0x5: decode FUNCTION_LO { - format SetInstructions{ - 0x2: slt({{ }}); - 0x3: sltu({{ }}); - } - }; - - 0x6: decode FUNCTION_LO { - format Trap { - 0x0: tge({{ }}); - 0x1: tgeu({{ }}); - 0x2: tlt({{ }}); - 0x3: tltu({{ }}); - 0x4: teq({{ }}); - 0x6: tne({{ }}); - } - } - } - - 0x1: decode REGIMM_HI { - 0x0: decode REGIMM_LO { - format Branch { - 0x0: bltz({{ }}); - 0x1: bgez({{ }}); - - //MIPS obsolete instructions - 0x2: bltzl({{ }}); - 0x3: bgezl({{ }}); - } - } - - 0x1: decode REGIMM_LO { - format Trap { - 0x0: tgei({{ }}); - 0x1: tgeiu({{ }}); - 0x2: tlti({{ }}); - 0x3: tltiu({{ }}); - 0x4: teqi({{ }}); - 0x6: tnei({{ }}); - } - } - - 0x2: decode REGIMM_LO { - format Branch { - 0x0: bltzal({{ }}); - 0x1: bgezal({{ }}); - - //MIPS obsolete instructions - 0x2: bltzall({{ }}); - 0x3: bgezall({{ }}); - } - } - - 0x3: decode REGIMM_LO { - 0x7: synci({{ }}); - } - } - - format Jump { - 0x2: j({{ }}); - 0x3: jal({{ }}); - } - - format Branch { - 0x4: beq({{ }}); - 0x5: bne({{ }}); - 0x6: blez({{ }}); - 0x7: bgtz({{ }}); - } - }; - - 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ - format IntImmediate { - 0x0: addi({{ }}); - 0x1: addiu({{ }}); - 0x2: slti({{ }}); - 0x3: sltiu({{ }}); - 0x4: andi({{ }}); - 0x5: ori({{ }}); - 0x6: xori({{ }}); - 0x7: lui({{ }}); - }; - }; - - 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ - - //Table A-11 MIPS32 COP0 Encoding of rs Field - 0x0: decode RS_MSB { - 0x0: decode RS { - 0x0: mfc0({{ }}); - 0xC: mtc0({{ }}); - 0xA: rdpgpr({{ }}); - - 0xB: decode SC { - 0x0: di({{ }}); - 0x1: ei({{ }}); - } - - 0xE: wrpgpr({{ }}); - } - - //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO - 0x1: decode FUNCTION { - 0x01: tlbr({{ }}); - 0x02: tlbwi({{ }}); - 0x06: tlbwr({{ }}); - 0x08: tlbp({{ }}); - 0x18: eret({{ }}); - 0x1F: deret({{ }}); - 0x20: wait({{ }}); - } - } - - //Table A-13 MIPS32 COP1 Encoding of rs Field - 0x1: decode RS_MSB { - - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: mfc1({{ }}); - 0x2: cfc1({{ }}); - 0x3: mfhc1({{ }}); - 0x4: mtc1({{ }}); - 0x6: ctc1({{ }}); - 0x7: mftc1({{ }}); - } - - 0x1: decode ND { - 0x0: decode TF { - 0x0: bc1f({{ }}); - 0x1: bc1t({{ }}); - } - - 0x1: decode TF { - 0x0: bc1fl({{ }}); - 0x1: bc1tl({{ }}); - } - } - } - - 0x1: decode RS_HI { - 0x2: decode RS_LO { - - //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S - //(( single-word )) - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x3: div_fmt({{ }}); - 0x4: sqrt_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x1: decode RS_LO { - //only legal for 64 bit - format mode64 { - 0x0: round_l({{ }}); - 0x1: trunc_l({{ }}); - 0x2: ceil_l({{ }}); - 0x3: floor_l({{ }}); - } - - 0x4: round_w({{ }}); - 0x5: trunc_w({{ }}); - 0x6: ceil_w({{ }}); - 0x7: floor_w({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - 0x2: movz({{ }}); - 0x3: movn({{ }}); - - format mode64 { - 0x2: recip({{ }}); - 0x3: rsqrt{{ }}); - } - } - - 0x4: decode RS_LO { - 0x1: cvt_d({{ }}); - 0x4: cvt_w({{ }}); - - //only legal for 64 bit - format mode64 { - 0x5: cvt_l({{ }}); - 0x6: cvt_ps({{ }}); - } - } - } - - //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D - 0x1: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x3: div_fmt({{ }}); - 0x4: sqrt_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x1: decode RS_LO { - //only legal for 64 bit - format mode64 { - 0x0: round_l({{ }}); - 0x1: trunc_l({{ }}); - 0x2: ceil_l({{ }}); - 0x3: floor_l({{ }}); - } - - 0x4: round_w({{ }}); - 0x5: trunc_w({{ }}); - 0x6: ceil_w({{ }}); - 0x7: floor_w({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - 0x2: movz({{ }}); - 0x3: movn({{ }}); - - format mode64 { - 0x5: recip({{ }}); - 0x6: rsqrt{{ }}); - } - } - - 0x4: decode RS_LO { - 0x0: cvt_s({{ }}); - 0x4: cvt_w({{ }}); - - //only legal for 64 bit - format mode64 { - 0x5: cvt_l({{ }}); - } - } - } - - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W - 0x4: decode FUNCTION { - 0x10: cvt_s({{ }}); - 0x10: cvt_d({{ }}); - } - - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 - //Note: "1. Format type L is legal only if 64-bit floating point operations - //are enabled." - 0x5: decode FUNCTION_HI { - 0x10: cvt_s({{ }}); - 0x11: cvt_d({{ }}); - } - - //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 - //Note: "1. Format type PS is legal only if 64-bit floating point operations - //are enabled. " - 0x6: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - 0x2: movz({{ }}); - 0x3: movn({{ }}); - } - - 0x4: decode RS_LO { - 0x0: cvt_s_pu({{ }}); - } - - 0x5: decode RS_LO { - 0x0: cvt_s_pl({{ }}); - 0x4: pll_s_pl({{ }}); - 0x5: plu_s_pl({{ }}); - 0x6: pul_s_pl({{ }}); - 0x7: puu_s_pl({{ }}); - } - } - } - - //Table A-19 MIPS32 COP2 Encoding of rs Field - 0x2: decode RS_MSB { - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: mfc2({{ }}); - 0x2: cfc2({{ }}); - 0x3: mfhc2({{ }}); - 0x4: mtc2({{ }}); - 0x6: ctc2({{ }}); - 0x7: mftc2({{ }}); - } - - 0x1: decode ND { - 0x0: decode TF { - 0x0: bc2f({{ }}); - 0x1: bc2t({{ }}); - } - - 0x1: decode TF { - 0x0: bc2fl({{ }}); - 0x1: bc2tl({{ }}); - } - } - } - } - - //Table A-20 MIPS64 COP1X Encoding of Function Field 1 - //Note: "COP1X instructions are legal only if 64-bit floating point - //operations are enabled." - 0x3: decode FUNCTION_HI { - 0x0: decode FUNCTION_LO { - 0x0: lwxc1({{ }}); - 0x1: ldxc1({{ }}); - 0x5: luxc1({{ }}); - } - - 0x1: decode FUNCTION_LO { - 0x0: swxc1({{ }}); - 0x1: sdxc1({{ }}); - 0x5: suxc1({{ }}); - 0x7: prefx({{ }}); - } - - 0x3: alnv_ps({{ }}); - - 0x4: decode FUNCTION_LO { - 0x0: madd_s({{ }}); - 0x1: madd_d({{ }}); - 0x6: madd_ps({{ }}); - } - - 0x5: decode FUNCTION_LO { - 0x0: msub_s({{ }}); - 0x1: msub_d({{ }}); - 0x6: msub_ps({{ }}); - } - - 0x6: decode FUNCTION_LO { - 0x0: nmadd_s({{ }}); - 0x1: nmadd_d({{ }}); - 0x6: nmadd_ps({{ }}); - } - - 0x7: decode FUNCTION_LO { - 0x0: nmsub_s({{ }}); - 0x1: nmsub_d({{ }}); - 0x6: nmsub_ps({{ }}); - } - } - - //MIPS obsolete instructions - 0x4: beql({{ }}); - 0x5: bnel({{ }}); - 0x6: blezl({{ }}); - 0x7: bgtzl({{ }}); - }; - - 0x3: decode OPCODE_LO default FailUnimpl::reserved(){ - - //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field - 0x4: decode FUNCTION_HI { - - 0x0: decode FUNCTION_LO { - 0x0: madd({{ }}); - 0x1: maddu({{ }}); - 0x2: mult({{ }}); - 0x4: msub({{ }}); - 0x5: msubu({{ }}); - } - - 0x4: decode FUNCTION_LO { - 0x0: clz({{ }}); - 0x1: clo({{ }}); - } - - 0x7: decode FUNCTION_LO { - 0x7: sdbbp({{ }}); - } - } - - //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture - 0x7: decode FUNCTION_HI { - - 0x0: decode FUNCTION_LO { - 0x1: ext({{ }}); - 0x4: ins({{ }}); - } - - //Table A-10 MIPS32 BSHFL Encoding of sa Field - 0x4: decode SA { - 0x02: wsbh({{ }}); - 0x10: seb({{ }}); - 0x18: seh({{ }}); - } - - 0x6: decode FUNCTION_LO { - 0x7: rdhwr({{ }}); - } - } - }; - - 0x4: decode OPCODE_LO default FailUnimpl::reserved(){ - format LoadMemory{ - 0x0: lb({{ }}); - 0x1: lh({{ }}); - 0x2: lwl({{ }}); - 0x3: lw({{ }}); - 0x4: lbu({{ }}); - 0x5: lhu({{ }}); - 0x6: lhu({{ }}); - }; - - 0x7: FailUnimpl::reserved({{ }}); - }; - - 0x5: decode OPCODE_LO default FailUnimpl::reserved(){ - format StoreMemory{ - 0x0: sb({{ }}); - 0x1: sh({{ }}); - 0x2: swl({{ }}); - 0x3: sw({{ }}); - 0x6: swr({{ }}); - }; - - format FailUnimpl{ - 0x4: reserved({{ }}); - 0x5: reserved({{ }}); - 0x7: cache({{ }}); - }; - - }; - - 0x6: decode OPCODE_LO default FailUnimpl::reserved(){ - format LoadMemory{ - 0x0: ll({{ }}); - 0x1: lwc1({{ }}); - 0x5: ldc1({{ }}); - }; - }; - - 0x7: decode OPCODE_LO default FailUnimpl::reserved(){ - format StoreMemory{ - 0x0: sc({{ }}); - 0x1: swc1({{ }}); - 0x5: sdc1({{ }}); - }; - - } -} - - diff --git a/arch/mips/isa_desc/formats.h b/arch/mips/isa_desc/formats.h deleted file mode 100644 index 404314c7a..000000000 --- a/arch/mips/isa_desc/formats.h +++ /dev/null @@ -1,22 +0,0 @@ -//Include the basic format -//Templates from this format are used later -##include "m5/arch/mips/isa_desc/formats/basic.format" - -//Include the integerOp and integerOpCc format -##include "m5/arch/mips/isa_desc/formats/integerop.format" - -//Include the floatOp format -##include "m5/arch/mips/isa_desc/formats/floatop.format" - -//Include the mem format -##include "m5/arch/mips/isa_desc/formats/mem.format" - -//Include the trap format -##include "m5/arch/mips/isa_desc/formats/trap.format" - -//Include the branch format -##include "m5/arch/mips/isa_desc/formats/branch.format" - -//Include the noop format -##include "m5/arch/mips/isa_desc/formats/noop.format" - diff --git a/arch/mips/isa_desc/formats/basic.format b/arch/mips/isa_desc/formats/basic.format deleted file mode 100644 index 8fba9845a..000000000 --- a/arch/mips/isa_desc/formats/basic.format +++ /dev/null @@ -1,65 +0,0 @@ - -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; -}}; - -// Basic instruction class declaration template. -def template BasicDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s - { - public: - /// Constructor. - %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s - }; -}}; - -// Basic instruction class constructor template. -def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) - { - %(constructor)s; - } -}}; - -// Basic instruction class execute method template. -def template BasicExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - Fault fault = No_Fault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(code)s; - - if(fault == No_Fault) - { - %(op_wb)s; - } - return fault; - } -}}; - -// Basic decode template. -def template BasicDecode {{ - return new %(class_name)s(machInst); -}}; - -// Basic decode template, passing mnemonic in as string arg to constructor. -def template BasicDecodeWithMnemonic {{ - return new %(class_name)s("%(mnemonic)s", machInst); -}}; - -// The most basic instruction format... used only for a few misc. insts -def format BasicOperate(code, *flags) {{ - iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; diff --git a/arch/mips/isa_desc/formats/branch.format b/arch/mips/isa_desc/formats/branch.format deleted file mode 100644 index 5327f30e8..000000000 --- a/arch/mips/isa_desc/formats/branch.format +++ /dev/null @@ -1,66 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Branch instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class Branch : public MipsStaticInst - { - protected: - - /// Constructor - Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template BranchExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Attempt to execute the instruction - try - { - checkPriv; - - %(op_decl)s; - %(op_rd)s; - %(code)s; - } - //If we have an exception for some reason, - //deal with it - catch(MipsException except) - { - //Deal with exception - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Branch(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = BranchExecute.subst(iop) -}}; diff --git a/arch/mips/isa_desc/formats/integerop.format b/arch/mips/isa_desc/formats/integerop.format deleted file mode 100644 index 6fa7feed3..000000000 --- a/arch/mips/isa_desc/formats/integerop.format +++ /dev/null @@ -1,110 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Integer operate instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class IntegerOp : public MipsStaticInst - { - protected: - - /// Constructor - IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template IntegerExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //These are set to constants when the execute method - //is generated - bool useCc = ; - bool checkPriv = ; - - //Attempt to execute the instruction - try - { - checkPriv; - - %(op_decl)s; - %(op_rd)s; - %(code)s; - } - //If we have an exception for some reason, - //deal with it - catch(MipsException except) - { - //Deal with exception - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - if(useCc) - { - xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); - xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); - xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; - xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; - xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); - xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); - xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; - xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; - } - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format IntegerOp(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', '0'), ('icValue', '0'), - ('xvValue', '0'), ('xcValue', '0')): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) -}}; - -// Primary format for integer operate instructions: -def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), - ('xvValue', xvValue), ('xcValue', xcValue)): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) -}}; diff --git a/arch/mips/isa_desc/formats/mem.format b/arch/mips/isa_desc/formats/mem.format deleted file mode 100644 index 5ed5237c5..000000000 --- a/arch/mips/isa_desc/formats/mem.format +++ /dev/null @@ -1,78 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Mem instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class Mem : public MipsStaticInst - { - protected: - - /// Constructor - Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template MemExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Attempt to execute the instruction - try - { - - %(op_decl)s; - %(op_rd)s; - ea_code - %(code)s; - } - //If we have an exception for some reason, - //deal with it - catch(MipsException except) - { - //Deal with exception - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Mem(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = MemExecute.subst(iop) - exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); -}}; - -def format Cas(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = MemExecute.subst(iop) - exec_output.replace('ea_code', 'EA = R1;'); -}}; diff --git a/arch/mips/isa_desc/formats/noop.format b/arch/mips/isa_desc/formats/noop.format deleted file mode 100644 index b1ece654d..000000000 --- a/arch/mips/isa_desc/formats/noop.format +++ /dev/null @@ -1,47 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Noop instruction -// - -output header {{ - /** - * Base class for integer operations. - */ - class Noop : public MipsStaticInst - { - protected: - - /// Constructor - Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template NoopExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Nothing to see here, move along - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Noop(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = NoopExecute.subst(iop) -}}; diff --git a/arch/mips/isa_desc/formats/trap.format b/arch/mips/isa_desc/formats/trap.format deleted file mode 100644 index 78f8d87b0..000000000 --- a/arch/mips/isa_desc/formats/trap.format +++ /dev/null @@ -1,53 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Trap instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class Trap : public MipsStaticInst - { - protected: - - /// Constructor - Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template TrapExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Call into the trap handler with the appropriate fault - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Trap(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = TrapExecute.subst(iop) -}}; diff --git a/arch/mips/isa_desc/includes.h b/arch/mips/isa_desc/includes.h deleted file mode 100644 index ff7cb7d1d..000000000 --- a/arch/mips/isa_desc/includes.h +++ /dev/null @@ -1,40 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Output include file directives. -// - -output header {{ -#include -#include -#include - -#include "cpu/static_inst.hh" -#include "traps.hh" -#include "mem/mem_req.hh" // some constructors use MemReq flags -}}; - -output decoder {{ -#include "base/cprintf.hh" -#include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" // for Jump::branchTarget() - -#include -#if defined(linux) -#include -#endif -}}; - -output exec {{ -#include -#if defined(linux) -#include -#endif - -#ifdef FULL_SYSTEM -//#include "arch/alpha/pseudo_inst.hh" -#endif -#include "cpu/base.hh" -#include "cpu/exetrace.hh" -#include "sim/sim_exit.hh" -}}; - diff --git a/arch/mips/isa_desc/operands.h b/arch/mips/isa_desc/operands.h deleted file mode 100644 index 77de6c9c4..000000000 --- a/arch/mips/isa_desc/operands.h +++ /dev/null @@ -1,33 +0,0 @@ -def operand_types {{ - 'sb' : ('signed int', 8), - 'ub' : ('unsigned int', 8), - 'shw' : ('signed int', 16), - 'uhw' : ('unsigned int', 16), - 'sw' : ('signed int', 32), - 'uw' : ('unsigned int', 32), - 'sdw' : ('signed int', 64), - 'udw' : ('unsigned int', 64), - 'sf' : ('float', 32), - 'df' : ('float', 64), - 'qf' : ('float', 128) -}}; - -def operands {{ - # Int regs default to unsigned, but code should not count on this. - # For clarity, descriptions that depend on unsigned behavior should - # explicitly specify '.uq'. - 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1), - 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2), - 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3), - #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), - #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), - #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), - 'Mem': MemOperandTraits('udw', None, - ('IsMemRef', 'IsLoad', 'IsStore'), 4) - #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), - #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), - #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), - # The next two are hacks for non-full-system call-pal emulation - #'R0': IntRegOperandTraits('uq', '0', None, 1), - #'R16': IntRegOperandTraits('uq', '16', None, 1) -}}; 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