From f97164aa29ad50c1b324416c14f93e0b463bcfa7 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 31 Oct 2018 16:45:48 +0000 Subject: arch-arm: Implement AArch32 RVBAR RVBAR has been added to the system register list since ARMv8.0-A. It is implemented only if the highest Exception Level is different (minor) than EL3. If that's not the case, MVBAR is used. Since the two registers are mutually exclusive (depending on the presence of EL3), they share the same coprocessor numbers: p15, 0, c12, c0, 1 Rather than introducing a new register alias, we overload MVBAR so that it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR). N.B MVBAR is RW, whereas RVBAR is RO Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/13999 Maintainer: Andreas Sandberg --- src/arch/arm/isa.hh | 5 +++++ src/arch/arm/miscregs.cc | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 89c673e4b..65d2251f8 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -229,6 +229,11 @@ namespace ArmISA privNonSecure(v); return *this; } + chain privRead(bool v = true) const { + privSecureRead(v); + privNonSecureRead(v); + return *this; + } chain hypRead(bool v = true) const { info[MISCREG_HYP_RD] = v; return *this; diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index ebe72dd52..1eee78116 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -3165,7 +3165,10 @@ ISA::initializeMiscRegMetadata() .bankedChild() .secure().exceptUserMode(); InitReg(MISCREG_MVBAR) - .mon().secure().exceptUserMode(); + .mon().secure() + .hypRead(FullSystem && system->highestEL() == EL2) + .privRead(FullSystem && system->highestEL() == EL1) + .exceptUserMode(); InitReg(MISCREG_RMR) .unimplemented() .mon().secure().exceptUserMode(); -- cgit v1.2.3