From c59f9456b9ee1d821416761de07759e0402c101c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 10 Apr 2007 17:13:26 +0000 Subject: Fix up the base x86 fault object and create a fault to be generated by unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't. --HG-- extra : convert_revision : 24e69c5a6a0af2d0cf67e858a051ae6624bb300f --- src/arch/x86/faults.hh | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh index 6d89c273a..8c9afcdb5 100644 --- a/src/arch/x86/faults.hh +++ b/src/arch/x86/faults.hh @@ -65,12 +65,32 @@ namespace X86ISA { class X86Fault : public FaultBase { + protected: + const char * name() + { + return "generic_x86_fault"; + } + void invoke(ThreadContext * tc) { panic("X86 faults are not implemented!"); } }; + class UnimpInstFault : public FaultBase + { + public: + const char * name() + { + return "unimplemented_micro"; + } + + void invoke(ThreadContext * tc) + { + panic("Unimplemented instruction!"); + } + }; + static inline Fault genPageTableFault(Addr va) { panic("Page table fault not implemented in x86!\n"); -- cgit v1.2.3 From 1320e294fe43dd6b0c90ab952e9bef473d8c23c7 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 10 Apr 2007 17:14:51 +0000 Subject: Added a class which lets you manipulate all the strings returned by the parser as a unit. --HG-- extra : convert_revision : eec4b188b44b80cee643542bbd1aaa139cbc4ef0 --- src/arch/x86/isa/base.isa | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/arch/x86/isa/base.isa b/src/arch/x86/isa/base.isa index cd166b306..eba24f709 100644 --- a/src/arch/x86/isa/base.isa +++ b/src/arch/x86/isa/base.isa @@ -58,6 +58,38 @@ // Base class for sparc instructions, and some support functions // +let {{ + # This class will help make dealing with output a little less verbose + class OutputBlocks(object): + def __init__(self, header_output="", + decoder_output="", + decode_block="", + exec_output=""): + self.header_output = header_output + self.decoder_output = decoder_output + self.decode_block = decode_block + self.exec_output = exec_output + + def append(self, blocks): + if isinstance(blocks, list) or isinstance(blocks, tuple): + assert(len(blocks) == 4) + self.header_output += blocks[0] + self.decoder_output += blocks[1] + self.decode_block += blocks[2] + self.exec_output += blocks[3] + else: + self.header_output += blocks.header_output + self.decoder_output += blocks.decoder_output + self.decode_block += blocks.decode_block + self.exec_output += blocks.exec_output + + def makeList(self): + return (self.header_output, + self.decoder_output, + self.decode_block, + self.exec_output) +}}; + output header {{ /** -- cgit v1.2.3 -- cgit v1.2.3 -- cgit v1.2.3 From b79cacaf3f317da084798307784a6193ec4c0e72 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 10 Apr 2007 17:22:45 +0000 Subject: Changed some instruction names to be in all caps, and "implemented" move to test the stub code for instructions. --HG-- extra : convert_revision : a377daf20545dfcbb0f97d8cafbe3d68416dc4b2 --- src/arch/x86/isa/decoder/one_byte_opcodes.isa | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index fed6dda28..4e044363b 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -61,11 +61,11 @@ 0x1: decode OPCODE_OP_TOP5 { format WarnUnimpl { 0x00: decode OPCODE_OP_BOTTOM3 { - 0x4: Inst::add(rAl,Ib); - 0x5: Inst::add(rAx,Iz); + 0x4: Inst::ADD(rAl,Ib); + 0x5: Inst::ADD(rAx,Iz); 0x6: push_ES(); 0x7: pop_ES(); - default: MultiInst::add(OPCODE_OP_BOTTOM3, + default: MultiInst::ADD(OPCODE_OP_BOTTOM3, [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); } 0x01: decode OPCODE_OP_BOTTOM3 { @@ -123,12 +123,12 @@ 0x7: das(); } 0x06: decode OPCODE_OP_BOTTOM3 { - 0x4: Inst::xor(rAl,Ib); - 0x5: Inst::xor(rAx,Iz); + 0x4: Inst::XOR(rAl,Ib); + 0x5: Inst::XOR(rAx,Iz); 0x6: M5InternalError::error( {{"Tried to execute the SS segment override prefix!"}}); 0x7: aaa(); - default: MultiInst::xor(OPCODE_OP_BOTTOM3, + default: MultiInst::XOR(OPCODE_OP_BOTTOM3, [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); } 0x07: decode OPCODE_OP_BOTTOM3 { @@ -237,11 +237,11 @@ 0x7: xchg_Ev_Gv(); } 0x11: decode OPCODE_OP_BOTTOM3 { - 0x0: mov_Eb_Gb(); - 0x1: mov_Ev_Gv(); - 0x2: mov_Gb_Eb(); - 0x3: mov_Gv_Ev(); - 0x4: mov_MwRv_Sw(); + 0x0: Inst::MOV(); //mov_Eb_Gb(); + 0x1: Inst::MOV(); //mov_Ev_Gv(); + 0x2: Inst::MOV(); //mov_Gb_Eb(); + 0x3: Inst::MOV(); //mov_Gv_Ev(); + 0x4: Inst::MOV(); //mov_MwRv_Sw(); 0x5: lea_Gv_M(); 0x6: mov_Sw_MwRv(); 0x7: group10_Ev(); //Make sure this is Ev -- cgit v1.2.3 -- cgit v1.2.3 From 9f4ebf915608403715bfb349a8871d4316e4a0c9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 10 Apr 2007 17:25:15 +0000 Subject: Reworked x86 a bit --HG-- extra : convert_revision : def1a30e54b59c718c451a631a1be6f8e787e843 --- src/arch/x86/isa/formats/multi.isa | 4 +-- src/arch/x86/isa/macroop.isa | 51 +++++++++++++++++++++++++++++--------- src/arch/x86/isa/microasm.isa | 21 +++++++++------- src/arch/x86/isa/microops/base.isa | 49 +++++++++++++++++++++++++----------- src/arch/x86/isa/specialize.isa | 38 +++++++++++----------------- 5 files changed, 102 insertions(+), 61 deletions(-) diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 7ad5ecd48..8f91c249c 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -72,7 +72,7 @@ def format Inst(*opTypeSet) {{ (header_output, decoder_output, decode_block, - exec_output) = doInst(name, Name, list(opTypeSet)) + exce_output) = doInst(name, Name, list(opTypeSet)).makeList() }}; def format MultiInst(switchVal, *opTypeSets) {{ @@ -82,5 +82,5 @@ def format MultiInst(switchVal, *opTypeSets) {{ (header_output, decoder_output, decode_block, - exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher) + exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher).makeList() }}; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 7d41a2dea..663ec7aee 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -55,26 +55,30 @@ // // Authors: Gabe Black +////////////////////////////////////////////////////////////////////////////// +// +// Architecture independent +// + // Execute method for macroops. def template MacroExecPanic {{ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Tried to execute macroop directly!"); - M5_DUMMY_RETURN + return NoFault; } }}; output header {{ - // Base class for most macroops, except ones that need to commit as - // they go. - class X86MacroInst : public StaticInst + // Base class for macroops + class MacroOp : public StaticInst { protected: const uint32_t numMicroOps; //Constructor. - X86MacroInst(const char *mnem, ExtMachInst _machInst, + MacroOp(const char *mnem, ExtMachInst _machInst, uint32_t _numMicroOps) : StaticInst(mnem, _machInst, No_OpClass), numMicroOps(_numMicroOps) @@ -84,7 +88,7 @@ output header {{ flags[IsMacroOp] = true; } - ~X86MacroInst() + ~MacroOp() { delete [] microOps; } @@ -97,10 +101,29 @@ output header {{ return microOps[microPC]; } + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + return mnemonic; + } + %(MacroExecPanic)s }; }}; +// Basic instruction class declaration template. +def template MacroDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor. + %(class_name)s(ExtMachInst machInst); + }; +}}; + // Basic instruction class constructor template. def template MacroConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) @@ -113,23 +136,27 @@ def template MacroConstructor {{ } }}; +////////////////////////////////////////////////////////////////////////////// +// +// X86 specific +// + let {{ def genMacroOp(name, Name, opSeq): - baseClass = 'X86MacroInst' - numMicroOps = len(opSeq.ops) + numMicroOps = len(opSeq) allocMicroOps = '' micropc = 0 - for op in opSeq.ops: + for op in opSeq: allocMicroOps += \ "microOps[%d] = %s;\n" % \ - (micropc, op.getAllocator(True, op.delayed, + (micropc, op.getAllocator('"' + name + '"', True, False, #op.delayed, micropc == 0, micropc == numMicroOps - 1)) micropc += 1 - iop = InstObjParams(name, Name, baseClass, + iop = InstObjParams(name, Name, 'MacroOp', {'code' : '', 'num_micro_ops' : numMicroOps, 'alloc_micro_ops' : allocMicroOps}) - header_output = BasicDeclare.subst(iop) + header_output = MacroDeclare.subst(iop) decoder_output = MacroConstructor.subst(iop) decode_block = BasicDecode.subst(iop) exec_output = '' diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 23567aae9..9d21b6bcc 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -85,7 +85,7 @@ let {{ text += ", false" return text - def getAllocator(self, *microFlags): + def getAllocator(self, mnemonic, *microFlags): args = '' signature = "<" emptySig = True @@ -104,7 +104,7 @@ let {{ else: raise Exception, "Unrecognized operand type." signature += ">" - return 'new %s%s(machInst%s%s)' % (self.className, signature, self.microFlagsText(microFlags), args) + return 'new %s%s(machInst, %s%s%s)' % (self.className, signature, mnemonic, self.microFlagsText(microFlags), args) }}; let{{ @@ -123,7 +123,7 @@ let{{ # the beginning of the line, so the previous component is stripped # before continuing. labelRe = re.compile(r'^[ \t]*(?P