From fce9c7a26f8c8a29d51c319c876a7bf0a32404a7 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 24 Apr 2019 17:19:23 -0700 Subject: mem: Remove the ISA specialized versions of port proxy's read/write. These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context. Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/alpha/linux/system.cc | 3 +- src/arch/alpha/stacktrace.cc | 14 ++++----- src/arch/arm/semihosting.cc | 30 +++++++++---------- src/arch/arm/stacktrace.cc | 6 ++-- src/arch/mips/stacktrace.cc | 7 ++--- src/arch/x86/stacktrace.cc | 6 ++-- src/kern/linux/helpers.cc | 10 +++++-- src/mem/port_proxy.hh | 67 +++++++++++------------------------------- src/sim/aux_vector.cc | 3 ++ 9 files changed, 60 insertions(+), 86 deletions(-) diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index 3ecf42f0b..33e760fe5 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -181,7 +181,8 @@ LinuxAlphaSystem::setDelayLoop(ThreadContext *tc) Tick cpuFreq = tc->getCpuPtr()->frequency(); assert(intrFreq); FSTranslatingPortProxy &vp = tc->getVirtProxy(); - vp.writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988)); + vp.write(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988), + GuestByteOrder); } } diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc index 3c302d27d..dfe74742e 100644 --- a/src/arch/alpha/stacktrace.cc +++ b/src/arch/alpha/stacktrace.cc @@ -54,23 +54,23 @@ ProcessInfo::ProcessInfo(ThreadContext *_tc) if (!symtab->findAddress("thread_info_size", addr)) panic("thread info not compiled into kernel\n"); - thread_info_size = vp.readGtoH(addr); + thread_info_size = vp.read(addr, GuestByteOrder); if (!symtab->findAddress("task_struct_size", addr)) panic("thread info not compiled into kernel\n"); - task_struct_size = vp.readGtoH(addr); + task_struct_size = vp.read(addr, GuestByteOrder); if (!symtab->findAddress("thread_info_task", addr)) panic("thread info not compiled into kernel\n"); - task_off = vp.readGtoH(addr); + task_off = vp.read(addr, GuestByteOrder); if (!symtab->findAddress("task_struct_pid", addr)) panic("thread info not compiled into kernel\n"); - pid_off = vp.readGtoH(addr); + pid_off = vp.read(addr, GuestByteOrder); if (!symtab->findAddress("task_struct_comm", addr)) panic("thread info not compiled into kernel\n"); - name_off = vp.readGtoH(addr); + name_off = vp.read(addr, GuestByteOrder); } Addr @@ -83,7 +83,7 @@ ProcessInfo::task(Addr ksp) const Addr tsk; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - tsk = vp.readGtoH(base + task_off); + tsk = vp.read(base + task_off, GuestByteOrder); return tsk; } @@ -98,7 +98,7 @@ ProcessInfo::pid(Addr ksp) const uint16_t pd; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - pd = vp.readGtoH(task + pid_off); + pd = vp.read(task + pid_off, GuestByteOrder); return pd; } diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc index 51107cbf7..3f9c0955c 100644 --- a/src/arch/arm/semihosting.cc +++ b/src/arch/arm/semihosting.cc @@ -176,7 +176,7 @@ ArmSemihosting::call64(ThreadContext *tc, uint32_t op, uint64_t param) DPRINTF(Semihosting, "Semihosting call64: %s(0x%x)\n", call->name, param); argv[0] = param; for (int i = 0; i < call->argc64; ++i) { - argv[i + 1] = proxy.readGtoH(param + i * 8, endian); + argv[i + 1] = proxy.read(param + i * 8, endian); DPRINTF(Semihosting, "\t: 0x%x\n", argv[i + 1]); } @@ -211,7 +211,7 @@ ArmSemihosting::call32(ThreadContext *tc, uint32_t op, uint32_t param) DPRINTF(Semihosting, "Semihosting call32: %s(0x%x)\n", call->name, param); argv[0] = param; for (int i = 0; i < call->argc32; ++i) { - argv[i + 1] = proxy.readGtoH(param + i * 4, endian); + argv[i + 1] = proxy.read(param + i * 4, endian); DPRINTF(Semihosting, "\t: 0x%x\n", argv[i + 1]); } @@ -556,9 +556,9 @@ ArmSemihosting::callGetCmdLine(ThreadContext *tc, bool aarch64, (const uint8_t *)cmdLine.c_str(), cmdLine.size() + 1); if (aarch64) - proxy.writeHtoG(argv[0] + 1 * 8, cmdLine.size(), endian); + proxy.write(argv[0] + 1 * 8, cmdLine.size(), endian); else - proxy.writeHtoG(argv[0] + 1 * 4, cmdLine.size(), endian); + proxy.write(argv[0] + 1 * 4, cmdLine.size(), endian); return retOK(0); } else { return retError(0); @@ -609,15 +609,15 @@ ArmSemihosting::callHeapInfo(ThreadContext *tc, bool aarch64, PortProxy &proxy = physProxy(tc); ByteOrder endian = ArmISA::byteOrder(tc); if (aarch64) { - proxy.writeHtoG(base + 0 * 8, heap_base, endian); - proxy.writeHtoG(base + 1 * 8, heap_limit, endian); - proxy.writeHtoG(base + 2 * 8, stack_base, endian); - proxy.writeHtoG(base + 3 * 8, stack_limit, endian); + proxy.write(base + 0 * 8, heap_base, endian); + proxy.write(base + 1 * 8, heap_limit, endian); + proxy.write(base + 2 * 8, stack_base, endian); + proxy.write(base + 3 * 8, stack_limit, endian); } else { - proxy.writeHtoG(base + 0 * 4, heap_base, endian); - proxy.writeHtoG(base + 1 * 4, heap_limit, endian); - proxy.writeHtoG(base + 2 * 4, stack_base, endian); - proxy.writeHtoG(base + 3 * 4, stack_limit, endian); + proxy.write(base + 0 * 4, heap_base, endian); + proxy.write(base + 1 * 4, heap_limit, endian); + proxy.write(base + 2 * 4, stack_base, endian); + proxy.write(base + 3 * 4, stack_limit, endian); } return retOK(0); @@ -666,10 +666,10 @@ ArmSemihosting::callElapsed(ThreadContext *tc, bool aarch64, const uint64_t tick = semiTick(curTick()); if (aarch64) { - proxy.writeHtoG(argv[0], tick, endian); + proxy.write(argv[0], tick, endian); } else { - proxy.writeHtoG(argv[0] + 0 * 4, tick, endian); - proxy.writeHtoG(argv[0] + 1 * 4, tick >> 32, endian); + proxy.write(argv[0] + 0 * 4, tick, endian); + proxy.write(argv[0] + 1 * 4, tick >> 32, endian); } return retOK(0); diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc index de5777554..b4dbf728b 100644 --- a/src/arch/arm/stacktrace.cc +++ b/src/arch/arm/stacktrace.cc @@ -54,7 +54,7 @@ readSymbol(ThreadContext *tc, const std::string name) if (!symtab->findAddress(name, addr)) panic("thread info not compiled into kernel\n"); - return vp.readGtoH(addr); + return vp.read(addr, GuestByteOrder); } ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc) @@ -76,7 +76,7 @@ ProcessInfo::task(Addr ksp) const Addr tsk; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - tsk = vp.readGtoH(base + task_off); + tsk = vp.read(base + task_off, GuestByteOrder); return tsk; } @@ -91,7 +91,7 @@ ProcessInfo::pid(Addr ksp) const uint16_t pd; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - pd = vp.readGtoH(task + pid_off); + pd = vp.read(task + pid_off, GuestByteOrder); return pd; } diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc index f584855dc..da492f12f 100644 --- a/src/arch/mips/stacktrace.cc +++ b/src/arch/mips/stacktrace.cc @@ -41,7 +41,6 @@ #include "mem/fs_translating_port_proxy.hh" #include "sim/system.hh" -using namespace std; using namespace MipsISA; ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc) @@ -57,7 +56,7 @@ ProcessInfo::task(Addr ksp) const Addr tsk; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - tsk = vp.readGtoH(base + task_off); + tsk = vp.read(base + task_off, GuestByteOrder); return tsk; } @@ -72,12 +71,12 @@ ProcessInfo::pid(Addr ksp) const uint16_t pd; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - pd = vp.readGtoH(task + pid_off); + pd = vp.read(task + pid_off, GuestByteOrder); return pd; } -string +std::string ProcessInfo::name(Addr ksp) const { Addr task = this->task(ksp); diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc index cdfd64b78..2d9eaea73 100644 --- a/src/arch/x86/stacktrace.cc +++ b/src/arch/x86/stacktrace.cc @@ -54,7 +54,7 @@ readSymbol(ThreadContext *tc, const std::string name) if (!symtab->findAddress(name, addr)) panic("thread info not compiled into kernel\n"); - return vp.readGtoH(addr); + return vp.read(addr, GuestByteOrder); } ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc) @@ -76,7 +76,7 @@ ProcessInfo::task(Addr ksp) const Addr tsk; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - tsk = vp.readGtoH(base + task_off); + tsk = vp.read(base + task_off, GuestByteOrder); return tsk; } @@ -91,7 +91,7 @@ ProcessInfo::pid(Addr ksp) const uint16_t pd; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - pd = vp.readGtoH(task + pid_off); + pd = vp.read(task + pid_off, GuestByteOrder); return pd; } diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc index 54fc42138..ed58427ec 100644 --- a/src/kern/linux/helpers.cc +++ b/src/kern/linux/helpers.cc @@ -43,6 +43,7 @@ #include "config/the_isa.hh" #include "cpu/thread_context.hh" #include "mem/fs_translating_port_proxy.hh" +#include "sim/byteswap.hh" #include "sim/system.hh" struct DmesgEntry { @@ -107,9 +108,12 @@ Linux::dumpDmesg(ThreadContext *tc, std::ostream &os) return; } - uint32_t log_buf_len = proxy.readGtoH(addr_lb_len); - uint32_t log_first_idx = proxy.readGtoH(addr_first); - uint32_t log_next_idx = proxy.readGtoH(addr_next); + uint32_t log_buf_len = + proxy.read(addr_lb_len, TheISA::GuestByteOrder); + uint32_t log_first_idx = + proxy.read(addr_first, TheISA::GuestByteOrder); + uint32_t log_next_idx = + proxy.read(addr_next, TheISA::GuestByteOrder); if (log_first_idx >= log_buf_len || log_next_idx >= log_buf_len) { warn("dmesg pointers/length corrupted\n"); diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh index fe87bf517..e48942e35 100644 --- a/src/mem/port_proxy.hh +++ b/src/mem/port_proxy.hh @@ -59,11 +59,6 @@ #ifndef __MEM_PORT_PROXY_HH__ #define __MEM_PORT_PROXY_HH__ -#include "config/the_isa.hh" -#if THE_ISA != NULL_ISA - #include "arch/isa_traits.hh" -#endif - #include "mem/port.hh" #include "sim/byteswap.hh" @@ -93,27 +88,34 @@ class PortProxy public: PortProxy(MasterPort &port, unsigned int cacheLineSize) : - _port(port), _cacheLineSize(cacheLineSize) { } + _port(port), _cacheLineSize(cacheLineSize) + {} virtual ~PortProxy() { } /** * Read size bytes memory at address and store in p. */ - virtual void readBlob(Addr addr, uint8_t* p, int size) const { + virtual void + readBlob(Addr addr, uint8_t* p, int size) const + { readBlobPhys(addr, 0, p, size); } /** * Write size bytes from p to address. */ - virtual void writeBlob(Addr addr, const uint8_t* p, int size) const { + virtual void + writeBlob(Addr addr, const uint8_t* p, int size) const + { writeBlobPhys(addr, 0, p, size); } /** * Fill size bytes starting at addr with byte value val. */ - virtual void memsetBlob(Addr addr, uint8_t v, int size) const { + virtual void + memsetBlob(Addr addr, uint8_t v, int size) const + { memsetBlobPhys(addr, 0, v, size); } @@ -149,33 +151,17 @@ class PortProxy /** * Read sizeof(T) bytes from address and return as object T. - * Performs selected endianness transform. - */ - template - T readGtoH(Addr address, ByteOrder guest_byte_order) const; - - /** - * Write object T to address. Writes sizeof(T) bytes. - * Performs selected endianness transform. - */ - template - void writeHtoG(Addr address, T data, ByteOrder guest_byte_order) const; - -#if THE_ISA != NULL_ISA - /** - * Read sizeof(T) bytes from address and return as object T. - * Performs Guest to Host endianness transform. + * Performs endianness conversion from the selected guest to host order. */ template - T readGtoH(Addr address) const; + T read(Addr address, ByteOrder guest_byte_order) const; /** * Write object T to address. Writes sizeof(T) bytes. - * Performs Host to Guest endianness transform. + * Performs endianness conversion from host to the selected guest order. */ template - void writeHtoG(Addr address, T data) const; -#endif + void write(Addr address, T data, ByteOrder guest_byte_order) const; }; @@ -214,7 +200,7 @@ PortProxy::write(Addr address, T data) const template T -PortProxy::readGtoH(Addr address, ByteOrder byte_order) const +PortProxy::read(Addr address, ByteOrder byte_order) const { T data; readBlob(address, (uint8_t*)&data, sizeof(T)); @@ -223,29 +209,10 @@ PortProxy::readGtoH(Addr address, ByteOrder byte_order) const template void -PortProxy::writeHtoG(Addr address, T data, ByteOrder byte_order) const +PortProxy::write(Addr address, T data, ByteOrder byte_order) const { data = htog(data, byte_order); writeBlob(address, (uint8_t*)&data, sizeof(T)); } -#if THE_ISA != NULL_ISA -template -T -PortProxy::readGtoH(Addr address) const -{ - T data; - readBlob(address, (uint8_t*)&data, sizeof(T)); - return TheISA::gtoh(data); -} - -template -void -PortProxy::writeHtoG(Addr address, T data) const -{ - data = TheISA::htog(data); - writeBlob(address, (uint8_t*)&data, sizeof(T)); -} -#endif - #endif // __MEM_PORT_PROXY_HH__ diff --git a/src/sim/aux_vector.cc b/src/sim/aux_vector.cc index 87a22e455..18834ac9b 100644 --- a/src/sim/aux_vector.cc +++ b/src/sim/aux_vector.cc @@ -66,6 +66,9 @@ #error "THE_ISA not set" #endif +#include "arch/isa_traits.hh" +#include "sim/byteswap.hh" + template AuxVector::AuxVector(IntType type, IntType val) : _auxType(TheISA::htog(type)), _auxVal(TheISA::htog(val)), -- cgit v1.2.3