From fcec1bf88c0f2e14f3c0c2dd59475757a7a6b00d Mon Sep 17 00:00:00 2001 From: Chuan Zhu Date: Mon, 15 Jan 2018 22:03:47 +0000 Subject: arch-arm: Correct masking of cp10 and cp11 in CPACR This patch fixes the masking of cp10 and cp11 in CPACR according to NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state, if EL3 is implemented and is using AArch32...", which is specified in ARM ARM. Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924 Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10044 Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index dfd523cf1..347e644d1 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2017 ARM Limited + * Copyright (c) 2010-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -400,7 +400,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) if (haveSecurity) { scr = readMiscRegNoEffect(MISCREG_SCR); cpsr = readMiscRegNoEffect(MISCREG_CPSR); - if (scr.ns && (cpsr.mode != MODE_MON)) { + if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); // NB: Skipping the full loop, here if (!nsacr.cp10) cpacrMask.cp10 = 0; @@ -745,7 +745,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) if (haveSecurity) { scr = readMiscRegNoEffect(MISCREG_SCR); CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); - if (scr.ns && (cpsr.mode != MODE_MON)) { + if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); // NB: Skipping the full loop, here if (!nsacr.cp10) cpacrMask.cp10 = 0; -- cgit v1.2.3