From 6c954de33ea598dfd356f315b3cea620acc3b8b7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 2 Aug 2004 17:10:02 -0400 Subject: added m5 debug and m5 switch cpu instruction (doesn't work yet) and a p4 memory/cpu config arch/alpha/alpha_memory.cc: Added code to fault on an unaligned access arch/alpha/isa_desc: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: Added m5debug break and m5switchcpu (the latter doesn't work) --HG-- extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916 --- arch/alpha/alpha_memory.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/alpha/alpha_memory.cc') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 5d9a5fc6f..9f5ab185e 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -491,6 +491,14 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const AlphaISA::mode_type mode = (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]); + + /* @todo this should actually be in there but for whatever reason + * Its not working at present. + */ + if (req->vaddr & (req->size - 1)) { + return Alignment_Fault; + } + if (PC_PAL(pc)) { mode = (req->flags & ALTMODE) ? (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE]) -- cgit v1.2.3