From 7b07b0877f05cffa93b782a76a15791c1126216a Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 2 Feb 2004 10:47:21 -0800 Subject: Change MemReqPtr parameters to references. This avoids incrementing and decrementing the MemReq reference counters on every call and return. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: cpu/exec_context.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: dev/alpha_console.cc: dev/alpha_console.hh: Change MemReqPtr parameters to references. --HG-- extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5 --- arch/alpha/alpha_memory.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/alpha/alpha_memory.cc') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index d934299b8..0f9ad2cfc 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const void -AlphaTlb::checkCacheability(MemReqPtr req) +AlphaTlb::checkCacheability(MemReqPtr &req) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address @@ -260,7 +260,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const Fault -AlphaItb::translate(MemReqPtr req) const +AlphaItb::translate(MemReqPtr &req) const { InternalProcReg *ipr = req->xc->regs.ipr; @@ -425,7 +425,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const } Fault -AlphaDtb::translate(MemReqPtr req, bool write) const +AlphaDtb::translate(MemReqPtr &req, bool write) const { RegFile *regs = &req->xc->regs; Addr pc = regs->pc; -- cgit v1.2.3