From 832a0917cf28d09520c1d2ac60921c4e034f7c26 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 24 Mar 2004 02:59:43 -0500 Subject: ULL() --HG-- extra : convert_revision : 543313ec248457e6cb2f8315881f030545e8cf45 --- arch/alpha/alpha_memory.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/alpha/alpha_memory.cc') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 2f0dcfecf..d1b152f73 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -92,7 +92,7 @@ AlphaTlb::checkCacheability(MemReqPtr &req) // IPR memory space not implemented if (!req->xc->misspeculating()) { switch (req->paddr) { - case 0xFFFFF00188: + case ULL(0xFFFFF00188): req->data = 0; break; -- cgit v1.2.3 From 782fb42992076dfd88ffb7d0c4e689d1bb1220d8 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Fri, 2 Apr 2004 22:57:08 -0800 Subject: Basic cleanup pass to get rid of a few things that made the Python configuration unnecessarily awkward. Biggest changes are: - External and internal object names now match in all cases. The macros still allow them to be different; the only reason I didn't get rid of that is that the macros themselves should be going away soon. In the few conflicting cases, I sometimes renamed the C++ object and sometimes renamed the config object. The latter sets of substitions are: s/BaseBus/Bus/; s/MemoryObject/FunctionalMemory/; s/MemoryControl/MemoryController/; s/FUPool/FuncUnitPool/; - SamplingCPU is temporarily broken... we need to change the model of how this works in the .ini file. Having it as a CPU proxy is really awkward. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: cpu/simple_cpu/simple_cpu.cc: sim/process.cc: Rename objects to match config name. cpu/base_cpu.cc: Uncomment SimObject define since SamplingCPU no longer does this for us. dev/ethertap.cc: Use unsigned instead of uint16_t for params. kern/tru64/tru64_system.cc: Use unsigned instead of uint64_t for init_param param. test/paramtest.cc: Fix old SimObjectParam. --HG-- extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc --- arch/alpha/alpha_memory.cc | 78 +++++++++++++++++++++++----------------------- 1 file changed, 39 insertions(+), 39 deletions(-) (limited to 'arch/alpha/alpha_memory.cc') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index d1b152f73..13cdb1d73 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -44,14 +44,14 @@ using namespace std; // // Alpha TLB // -AlphaTlb::AlphaTlb(const string &name, int s) +AlphaTLB::AlphaTLB(const string &name, int s) : SimObject(name), size(s), nlu(0) { table = new AlphaISA::PTE[size]; memset(table, 0, sizeof(AlphaISA::PTE[size])); } -AlphaTlb::~AlphaTlb() +AlphaTLB::~AlphaTLB() { if (table) delete [] table; @@ -59,7 +59,7 @@ AlphaTlb::~AlphaTlb() // look up an entry in the TLB AlphaISA::PTE * -AlphaTlb::lookup(Addr vpn, uint8_t asn) const +AlphaTLB::lookup(Addr vpn, uint8_t asn) const { DPRINTF(TLB, "lookup %#x\n", vpn); @@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const void -AlphaTlb::checkCacheability(MemReqPtr &req) +AlphaTLB::checkCacheability(MemReqPtr &req) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address @@ -111,7 +111,7 @@ AlphaTlb::checkCacheability(MemReqPtr &req) // insert a new TLB entry void -AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte) +AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte) { if (table[nlu].valid) { Addr oldvpn = table[nlu].tag; @@ -145,7 +145,7 @@ AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte) } void -AlphaTlb::flushAll() +AlphaTLB::flushAll() { memset(table, 0, sizeof(AlphaISA::PTE[size])); lookupTable.clear(); @@ -153,7 +153,7 @@ AlphaTlb::flushAll() } void -AlphaTlb::flushProcesses() +AlphaTLB::flushProcesses() { PageTable::iterator i = lookupTable.begin(); PageTable::iterator end = lookupTable.end(); @@ -173,7 +173,7 @@ AlphaTlb::flushProcesses() } void -AlphaTlb::flushAddr(Addr vaddr, uint8_t asn) +AlphaTLB::flushAddr(Addr vaddr, uint8_t asn) { Addr vpn = VA_VPN(vaddr); @@ -201,7 +201,7 @@ AlphaTlb::flushAddr(Addr vaddr, uint8_t asn) void -AlphaTlb::serialize(ostream &os) +AlphaTLB::serialize(ostream &os) { SERIALIZE_SCALAR(size); SERIALIZE_SCALAR(nlu); @@ -213,7 +213,7 @@ AlphaTlb::serialize(ostream &os) } void -AlphaTlb::unserialize(Checkpoint *cp, const string §ion) +AlphaTLB::unserialize(Checkpoint *cp, const string §ion) { UNSERIALIZE_SCALAR(size); UNSERIALIZE_SCALAR(nlu); @@ -231,13 +231,13 @@ AlphaTlb::unserialize(Checkpoint *cp, const string §ion) // // Alpha ITB // -AlphaItb::AlphaItb(const std::string &name, int size) - : AlphaTlb(name, size) +AlphaITB::AlphaITB(const std::string &name, int size) + : AlphaTLB(name, size) {} void -AlphaItb::regStats() +AlphaITB::regStats() { hits .name(name() + ".hits") @@ -256,7 +256,7 @@ AlphaItb::regStats() } void -AlphaItb::fault(Addr pc, ExecContext *xc) const +AlphaITB::fault(Addr pc, ExecContext *xc) const { uint64_t *ipr = xc->regs.ipr; @@ -269,7 +269,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const Fault -AlphaItb::translate(MemReqPtr &req) const +AlphaITB::translate(MemReqPtr &req) const { InternalProcReg *ipr = req->xc->regs.ipr; @@ -287,7 +287,7 @@ AlphaItb::translate(MemReqPtr &req) const if (!validVirtualAddress(req->vaddr)) { fault(req->vaddr, req->xc); acv++; - return Itb_Acv_Fault; + return ITB_Acv_Fault; } // Check for "superpage" mapping: when SP<1> is set, and @@ -299,7 +299,7 @@ AlphaItb::translate(MemReqPtr &req) const if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) { fault(req->vaddr, req->xc); acv++; - return Itb_Acv_Fault; + return ITB_Acv_Fault; } req->paddr = req->vaddr & PA_IMPL_MASK; @@ -311,7 +311,7 @@ AlphaItb::translate(MemReqPtr &req) const if (!pte) { fault(req->vaddr, req->xc); misses++; - return Itb_Fault_Fault; + return ITB_Fault_Fault; } req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3); @@ -321,7 +321,7 @@ AlphaItb::translate(MemReqPtr &req) const // instruction access fault fault(req->vaddr, req->xc); acv++; - return Itb_Acv_Fault; + return ITB_Acv_Fault; } hits++; @@ -341,12 +341,12 @@ AlphaItb::translate(MemReqPtr &req) const // // Alpha DTB // -AlphaDtb::AlphaDtb(const std::string &name, int size) - : AlphaTlb(name, size) +AlphaDTB::AlphaDTB(const std::string &name, int size) + : AlphaTLB(name, size) {} void -AlphaDtb::regStats() +AlphaDTB::regStats() { read_hits .name(name() + ".read_hits") @@ -415,7 +415,7 @@ AlphaDtb::regStats() } void -AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const +AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const { uint64_t *ipr = xc->regs.ipr; @@ -439,7 +439,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const } Fault -AlphaDtb::translate(MemReqPtr &req, bool write) const +AlphaDTB::translate(MemReqPtr &req, bool write) const { RegFile *regs = &req->xc->regs; Addr pc = regs->pc; @@ -553,7 +553,7 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const } AlphaISA::PTE & -AlphaTlb::index(bool advance) +AlphaTLB::index(bool advance) { AlphaISA::PTE *pte = &table[nlu]; @@ -563,43 +563,43 @@ AlphaTlb::index(bool advance) return *pte; } -BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb) +BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) Param size; -END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb) +END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) -BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb) +BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) INIT_PARAM_DFLT(size, "TLB size", 48) -END_INIT_SIM_OBJECT_PARAMS(AlphaItb) +END_INIT_SIM_OBJECT_PARAMS(AlphaITB) -CREATE_SIM_OBJECT(AlphaItb) +CREATE_SIM_OBJECT(AlphaITB) { - return new AlphaItb(getInstanceName(), size); + return new AlphaITB(getInstanceName(), size); } -REGISTER_SIM_OBJECT("AlphaITB", AlphaItb) +REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) -BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb) +BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) Param size; -END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb) +END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) -BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb) +BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) INIT_PARAM_DFLT(size, "TLB size", 64) -END_INIT_SIM_OBJECT_PARAMS(AlphaDtb) +END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) -CREATE_SIM_OBJECT(AlphaDtb) +CREATE_SIM_OBJECT(AlphaDTB) { - return new AlphaDtb(getInstanceName(), size); + return new AlphaDTB(getInstanceName(), size); } -REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb) +REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) -- cgit v1.2.3 From 65205b82acee56b0034c0122d5f5a89f57c760fc Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 3 Apr 2004 13:46:10 -0800 Subject: More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL). Also missed renames in a bunch of config files somehow. (See previous changeset for list of renames.) arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/faults.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/simple_cpu/simple_cpu.hh: More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL). --HG-- extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d --- arch/alpha/alpha_memory.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/alpha/alpha_memory.cc') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 13cdb1d73..dea25a440 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -465,7 +465,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const req->xc); if (write) { write_acv++; } else { read_acv++; } - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } // Check for "superpage" mapping: when SP<1> is set, and @@ -480,7 +480,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK), req->xc); if (write) { write_acv++; } else { read_acv++; } - return Dtb_Acv_Fault; + return DTB_Acv_Fault; } req->paddr = req->vaddr & PA_IMPL_MASK; @@ -512,13 +512,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const (pte->fonw ? MM_STAT_FONW_MASK : 0), req->xc); write_acv++; - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } if (pte->fonw) { fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK, req->xc); write_acv++; - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } } else { if (!(pte->xre & MODE2MASK(mode))) { @@ -527,12 +527,12 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const (pte->fonr ? MM_STAT_FONR_MASK : 0), req->xc); read_acv++; - return Dtb_Acv_Fault; + return DTB_Acv_Fault; } if (pte->fonr) { fault(req->vaddr, MM_STAT_FONR_MASK, req->xc); read_acv++; - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } } } -- cgit v1.2.3 From d4069233eb8cc875aa443cb7c6a16b748e3acc42 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 6 Apr 2004 10:02:00 -0700 Subject: Beta version of Python configuration tool. Generates .ini files from Python script description. arch/alpha/alpha_memory.cc: dev/io_device.cc: Add DEFINE_SIM_OBJECT_CLASS_NAME for intermediate SimObjects. test/paramtest.cc: Fix stupid spelling. --HG-- extra : convert_revision : dc020208cb6507c1afb1ed771a7218daba678e09 --- arch/alpha/alpha_memory.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/alpha/alpha_memory.cc') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index dea25a440..1608cc4a4 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -563,6 +563,8 @@ AlphaTLB::index(bool advance) return *pte; } +DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) + BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) Param size; -- cgit v1.2.3