From 12747d3084339d9db52d32e75215242b38474887 Mon Sep 17 00:00:00 2001 From: Andrew Schultz Date: Wed, 18 Feb 2004 21:38:55 -0500 Subject: Change the physical memory logic, and also add misspeculation fix to tlb index calls that are called from ExecContext::readIpr arch/alpha/ev5.cc: Fix misspeculation bugs for misspeculated IPR accesses --HG-- extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7 --- arch/alpha/ev5.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/alpha/ev5.cc') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 8494ee9f6..aaa81a58d 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -240,7 +240,9 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; - regs.intrlock = false; + + if (!misspeculating()) + regs.intrlock = false; break; case AlphaISA::IPR_VA_FORM: @@ -253,7 +255,7 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_DTB_PTE: { - AlphaISA::PTE &pte = dtb->index(); + AlphaISA::PTE &pte = dtb->index(!misspeculating()); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; -- cgit v1.2.3 From c79deda8cd404565bbd277e67b3533b6c13fac74 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 28 Feb 2004 17:21:32 -0500 Subject: Fix handling of rpcc in full-system mode. arch/alpha/ev5.cc: Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently. (Very slightly). arch/alpha/isa_desc: Upper half of rpcc result comes from value written to IPR_CC, not actual cycle counter. --HG-- extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125 --- arch/alpha/ev5.cc | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/alpha/ev5.cc') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index aaa81a58d..96c51a2aa 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -329,13 +329,25 @@ ExecContext::setIpr(int idx, uint64_t val) case AlphaISA::IPR_PAL_BASE: case AlphaISA::IPR_IC_PERR_STAT: case AlphaISA::IPR_DC_PERR_STAT: - case AlphaISA::IPR_CC_CTL: - case AlphaISA::IPR_CC: case AlphaISA::IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; + case AlphaISA::IPR_CC_CTL: + // This IPR resets the cycle counter. We assume this only + // happens once... let's verify that. + assert(ipr[idx] == 0); + ipr[idx] = 1; + break; + + case AlphaISA::IPR_CC: + // This IPR only writes the upper 64 bits. It's ok to write + // all 64 here since we mask out the lower 32 in rpcc (see + // isa_desc). + ipr[idx] = val; + break; + case AlphaISA::IPR_PALtemp23: // write entire quad w/ no side-effect ipr[idx] = val; -- cgit v1.2.3 From 27960f6d858e92572d37604e92747d0b45591665 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 29 Feb 2004 14:54:52 -0500 Subject: fix rpcc arch/alpha/ev5.cc: actually implement the cycle count register arch/alpha/isa_desc: the rpcc instruction really just reads the cycle count register --HG-- extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1 --- arch/alpha/ev5.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/alpha/ev5.cc') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 96c51a2aa..551cbdabf 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault) retval = ipr[idx]; break; + case AlphaISA::IPR_CC: + retval |= ipr[idx] & ULL(0xffffffff00000000); + retval |= curTick & ULL(0x00000000ffffffff); + break; + case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; -- cgit v1.2.3