From a896960cbfce76a0e0c8cfb5cbdfc805ce72577b Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Thu, 27 May 2004 17:46:16 -0400
Subject: FastCPU model added.  It's very similar to the SimpleCPU, just
 without a lot of the stats tracking. Also various changes to make the CPU
 model less ISA dependent, which includes moving the code that checks for
 interrupts up to the ISA level, moving code that zeroes the zero registers up
 to the ISA level, and removing opcode and ra from the regfile.

arch/alpha/alpha_memory.cc:
    The regfile has been changed so it no longer has the opcode and ra.  Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
    Moved code that once existed within simpleCPU to ev5, and templatized it.
    This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
    Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
    Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
    Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
    Removed opcode and ra from the regfile.  The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
    Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
    Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
    Added in a more generic trap function so "ev5_trap" doesn't need to be called.  It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
    Exec context now has the instruction within it.  Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
    Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
    Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
    Added declaration for execute() using FastCPUExecContext.

--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
---
 arch/alpha/ev5.cc | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

(limited to 'arch/alpha/ev5.cc')

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 9b3ac5fff..fe665abe6 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -6,6 +6,7 @@
 #include "sim/debug.hh"
 #endif
 #include "cpu/exec_context.hh"
+#include "cpu/fast_cpu/fast_cpu.hh"
 #include "sim/sim_events.hh"
 #include "targetarch/isa_traits.hh"
 #include "base/remote_gdb.hh"
@@ -100,6 +101,64 @@ AlphaISA::initIPRs(RegFile *regs)
 }
 
 
+template <class XC>
+void
+AlphaISA::processInterrupts(XC *xc)
+{
+    //Check if there are any outstanding interrupts
+    //Handle the interrupts
+    int ipl = 0;
+    int summary = 0;
+    IntReg *ipr = xc->getIprPtr();
+
+    check_interrupts = 0;
+
+    if (ipr[IPR_ASTRR])
+        panic("asynchronous traps not implemented\n");
+
+    if (ipr[IPR_SIRR]) {
+        for (int i = INTLEVEL_SOFTWARE_MIN;
+             i < INTLEVEL_SOFTWARE_MAX; i++) {
+            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    uint64_t interrupts = xc->intr_status();
+
+    if (interrupts) {
+        for (int i = INTLEVEL_EXTERNAL_MIN;
+             i < INTLEVEL_EXTERNAL_MAX; i++) {
+            if (interrupts & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = i;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    if (ipl && ipl > ipr[IPR_IPLR]) {
+        ipr[IPR_ISR] = summary;
+        ipr[IPR_INTID] = ipl;
+        xc->trap(Interrupt_Fault);
+        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+                ipr[IPR_IPLR], ipl, summary);
+    }
+
+}
+
+template <class XC>
+void
+AlphaISA::zeroRegisters(XC *xc)
+{
+    // Insure ISA semantics
+    xc->setIntReg(ZeroReg, 0);
+    xc->setFloatRegDouble(ZeroReg, 0.0);
+}
+
 void
 ExecContext::ev5_trap(Fault fault)
 {
@@ -585,4 +644,12 @@ ExecContext::simPalCheck(int palFunc)
     return true;
 }
 
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::processInterrupts(FastCPU *xc);
+
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::zeroRegisters(FastCPU *xc);
+
 #endif // FULL_SYSTEM
-- 
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