From e3fb3d1ad01aa08ab6631c3f77e6f105d5a736a6 Mon Sep 17 00:00:00 2001 From: Andrew Schultz Date: Thu, 19 Feb 2004 16:30:06 -0500 Subject: Misspeculation fix and (more importantly) change to allow for the ev6 style physical addressing. This has the uncacheable bit as bit 40 as opposed to bit 39. Additionally, we now support (at least superficially) a 44-bit physical address. To deal with superpage access in this scheme, any super page access with either bit 39 or 40 set is sign extended. --HG-- extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab --- arch/alpha/ev5.hh | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/alpha/ev5.hh') diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh index aa3d7e226..bd4115704 100644 --- a/arch/alpha/ev5.hh +++ b/arch/alpha/ev5.hh @@ -57,9 +57,10 @@ #define VA_SPACE(X) (((X) >> 41) & 0x3) #define VA_POFS(X) ((X) & 0x1fff) -#define PA_IMPL_MASK ULL(0xffffffffff) -#define PA_UNCACHED_BIT ULL(0x8000000000) -#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000)) +#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami +#define PA_UNCACHED_BIT_39 ULL(0x8000000000) +#define PA_UNCACHED_BIT_40 ULL(0x10000000000) +#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000)) #define PA_PFN2PA(X) ((X) << 13) -- cgit v1.2.3