From 309e1d81939c44f6b31795be84868605e05b09ec Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 16 May 2006 17:36:50 -0400 Subject: Split SimpleCPU into two different models, AtomicSimpleCPU and TimingSimpleCPU, which use atomic and timing memory accesses respectively. Common code is factored into the BaseSimpleCPU class. AtomicSimpleCPU includes an option (simulate_stalls) to add delays based on the estimated latency reported by the atomic accesses. Plain old "SimpleCPU" is gone; I have not updated all the config files (just test/test.py). Also fixes to get timing accesses working in new memory model and to get split-phase memory instruction definitions working with new memory model as well. arch/alpha/isa/main.isa: Need to include packet_impl.h for functions that use Packet objects. arch/alpha/isa/mem.isa: Change completeAcc() methods to take Packet object pointers. Also split out StoreCond template for completeAcc(), since that's the only one that needs write_result and we get an unused variable warning if we always have it in there. build/SConstruct: Update list of recognized CPU model names. configs/test/test.py: Change SimpleCPU to AtomicSimpleCPU. cpu/SConscript: Define sources for new CPU models. Add split memory access methods to CPU model signatures. cpu/cpu_models.py: cpu/static_inst.hh: Define new CPU models. cpu/simple/base.cc: cpu/simple/base.hh: Factor out pieces specific to Atomic or Timing models. mem/bus.cc: Bus needs to be able to route timing packets based on explicit dest so responses can get back to requester. Set dest to Packet::Broadcast to indicate that dest should be derived from address. Also set packet src field based on port from which packet is sent. mem/bus.hh: Set packet src field based on port from which packet is sent. mem/packet.hh: Define Broadcast destination address to indicate that packet should be routed based on address. mem/physical.cc: Set packet dest on response so packet is routed back to requester properly. mem/port.cc: Flag blob packets as Broadcast. python/m5/objects/PhysicalMemory.py: Change default latency to be 1 cycle. --HG-- rename : cpu/simple/cpu.cc => cpu/simple/base.cc rename : cpu/simple/cpu.hh => cpu/simple/base.hh extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132 --- arch/alpha/isa/mem.isa | 53 ++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 41 insertions(+), 12 deletions(-) (limited to 'arch/alpha/isa/mem.isa') diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa index 8742d308f..98c7ba979 100644 --- a/arch/alpha/isa/mem.isa +++ b/arch/alpha/isa/mem.isa @@ -178,7 +178,8 @@ def template InitiateAccDeclare {{ def template CompleteAccDeclare {{ - Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(Packet *, %(CPU_exec_context)s *, + Trace::InstRecord *) const; }}; @@ -304,7 +305,7 @@ def template LoadInitiateAcc {{ def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(uint8_t *data, + Fault %(class_name)s::completeAcc(Packet *pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -313,7 +314,7 @@ def template LoadCompleteAcc {{ %(fp_enable_check)s; %(op_decl)s; - memcpy(&Mem, data, sizeof(Mem)); + Mem = pkt->get(); if (fault == NoFault) { %(memacc_code)s; @@ -406,7 +407,6 @@ def template StoreInitiateAcc {{ { Addr EA; Fault fault = NoFault; - uint64_t write_result = 0; %(fp_enable_check)s; %(op_decl)s; @@ -419,7 +419,7 @@ def template StoreInitiateAcc {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, &write_result); + memAccessFlags, NULL); if (traceData) { traceData->setData(Mem); } } @@ -429,17 +429,39 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(uint8_t *data, + Fault %(class_name)s::completeAcc(Packet *pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - uint64_t write_result = 0; %(fp_enable_check)s; %(op_dest_decl)s; - memcpy(&write_result, data, sizeof(write_result)); + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + + +def template StoreCondCompleteAcc {{ + Fault %(class_name)s::completeAcc(Packet *pkt, + %(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(fp_enable_check)s; + %(op_dest_decl)s; + + uint64_t write_result = pkt->req->getScResult(); if (fault == NoFault) { %(postacc_code)s; @@ -505,7 +527,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(uint8_t *data, + Fault %(class_name)s::completeAcc(Packet *pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -577,7 +599,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, if (exec_template_base == 'Load'): initiateacc_cblk = CodeBlock(ea_code + memacc_code) completeacc_cblk = CodeBlock(memacc_code + postacc_code) - elif (exec_template_base == 'Store'): + elif (exec_template_base.startswith('Store')): initiateacc_cblk = CodeBlock(ea_code + memacc_code) completeacc_cblk = CodeBlock(postacc_code) else: @@ -595,7 +617,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, initiateacc_iop.memacc_code = memacc_cblk.code completeacc_iop.memacc_code = memacc_cblk.code completeacc_iop.postacc_code = postacc_cblk.code - elif (exec_template_base == 'Store'): + elif (exec_template_base.startswith('Store')): initiateacc_iop.ea_code = ea_cblk.code initiateacc_iop.memacc_code = memacc_cblk.code completeacc_iop.postacc_code = postacc_cblk.code @@ -616,6 +638,13 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, memacc_iop.constructor += s # select templates + + # define aliases... most StoreCond templates are the same as the + # corresponding Store templates (only CompleteAcc is different). + StoreCondMemAccExecute = StoreMemAccExecute + StoreCondExecute = StoreExecute + StoreCondInitiateAcc = StoreInitiateAcc + memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') fullExecTemplate = eval(exec_template_base + 'Execute') initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') @@ -685,7 +714,7 @@ def format StoreCond(memacc_code, postacc_code, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - postacc_code, exec_template_base = 'Store') + postacc_code, exec_template_base = 'StoreCond') }}; -- cgit v1.2.3