From c79deda8cd404565bbd277e67b3533b6c13fac74 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 28 Feb 2004 17:21:32 -0500 Subject: Fix handling of rpcc in full-system mode. arch/alpha/ev5.cc: Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently. (Very slightly). arch/alpha/isa_desc: Upper half of rpcc result comes from value written to IPR_CC, not actual cycle counter. --HG-- extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125 --- arch/alpha/isa_desc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/alpha/isa_desc') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 46fb306a4..c4d367211 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2388,7 +2388,14 @@ decode OPCODE default Unknown::unknown() { } format BasicOperate { - 0xc000: rpcc({{ Ra = curTick; }}); + 0xc000: rpcc({{ +#ifdef FULL_SYSTEM + uint64_t cc = xc->readIpr(AlphaISA::IPR_CC, fault); + Ra = (cc<63:32> | curTick<31:0>); +#else + Ra = curTick; +#endif + }}); // All of the barrier instructions below do nothing in // their execute() methods (hence the empty code blocks). -- cgit v1.2.3