From c7d6745b073982782eb05ca523b53e1c7fe784da Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 2 Nov 2003 02:07:31 -0500 Subject: deprecate the m5exit instruction and rename it to m5exit_old Implement a new m5exit instruction with an optional delay arch/alpha/isa_desc: move m5exit to m5exit old. The old version of the instruction is now deprecated Implement the new exit instruction with the optional delay sim/sim_events.cc: sim/sim_events.hh: Make SimExit take a cycle sim/universe.cc: provide ticksPerMS, ticksPerUS, and ticksPerNS so we don't have to do math during the cycle --HG-- extra : convert_revision : e2ed47a2e5cfcd57c82086c6fcb4a28bf801c214 --- arch/alpha/isa_desc | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/alpha/isa_desc') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 75f765029..09fb4a50a 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2425,9 +2425,21 @@ decode OPCODE default Unknown::unknown() { if (!xc->misspeculating()) Annotate::EndInterval(xc); }}, No_OpClass); - 0x20: m5exit({{ + 0x20: m5exit_old({{ if (!xc->misspeculating()) - SimExit("m5_exit instruction encountered"); + SimExit(curTick, "m5_exit_old instruction encountered"); + }}, No_OpClass); + 0x21: m5exit({{ + if (!xc->misspeculating()) { + Tick when = curTick; + Tick delay = xc->regs.intRegFile[16]; + if (delay != 0) { + delay *= ticksPerUS; + delay /= 1000; + when += delay; + } + SimExit(when, "m5_exit instruction encountered"); + } }}, No_OpClass); 0x30: initparam({{ Ra = xc->cpu->system->init_param; }}); 0x40: resetstats({{ -- cgit v1.2.3 From 780b3b4bcd575d5145204037901f751e01f42cd2 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 2 Nov 2003 13:01:08 -0500 Subject: SimExit takes a time now arch/alpha/isa_desc: regen --HG-- extra : convert_revision : a9da9d2a5fc8a0414491e437747cde48dfb61a20 --- arch/alpha/isa_desc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/alpha/isa_desc') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 09fb4a50a..aaf0cb0a7 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2364,7 +2364,7 @@ decode OPCODE default Unknown::unknown() { format EmulatedCallPal { 0x00: halt ({{ if (!xc->misspeculating()) - SimExit("halt instruction encountered"); + SimExit(curTick, "halt instruction encountered"); }}); 0x83: callsys({{ if (!xc->misspeculating()) -- cgit v1.2.3 From 667cbb6690b1f4af68ab7dad8caed8cdf107a090 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 2 Nov 2003 18:02:58 -0500 Subject: Implement more m5 pseduo opcodes: resetstats dumpstats dumpresetstats m5checkpoint Lots of cleanup of serialization and stats dumping/resetting to work with these new instructions arch/alpha/isa_desc: Implement more m5 pseduo opcodes: resetstats dumpstats dumpresetstats m5checkpoint All of these functions take two optional parameters, the first is a delay, and the second is a period. The delay tells the simulator to wait the specified number of nanoseconds before triggering the event, the period tells the simulator to repeat the event with a specified frequency base/statistics.cc: base/statistics.hh: regReset RegResetCallback dev/disk_image.cc: serializeFilename -> CheckpointFile() sim/debug.cc: Move this debugging statement to sim_stats.cc sim/eventq.cc: Don't AutoDelete an event if it is scheduled since the process() function could potentially schedule the event again. sim/main.cc: DumpStatsEvent is now Statistics::SetupEvent(Dump, curTick) sim/serialize.cc: Change the serialize event so that it's possible to cause the event to repeat. Also make the priority such that the event happens just before the simulator would exit if both events were scheduled for the same cycle. get rid of the serializeFilename variable and provide a CheckpointFile() function. This function takes a basename that is set in the configuration, and appends the current cycle to the name so that multiple checkpoints can be dumped from the same simulation. Also, don't exit the simulation when a checkpoint file is dumped. sim/serialize.hh: serializeFilename -> CheckpointFile() SetupCheckpoint function to tell the simulator to prepare to checkpoint at a certain time with a certain period sim/sim_events.cc: DumpStatsEvent stuff gets move to sim_stats.(cc|hh) The context stuff gets moved into the already existing stats context in stat_context.cc sim/sim_events.hh: DumpStatsEvent stuff gets move to sim_stats.(cc|hh) sim/universe.cc: Provide some simple functions for converting times into ticks. These use floating point math to get as close as possible to the real values. Multipliers are set up ahead of time --HG-- extra : convert_revision : d06ef26a9237529a1e5060cb1ac2dcc04d4ec252 --- arch/alpha/isa_desc | 56 +++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 8 deletions(-) (limited to 'arch/alpha/isa_desc') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index aaf0cb0a7..e34739b86 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -28,7 +28,9 @@ let {{ #include "cpu/simple_cpu/simple_cpu.hh" #include "cpu/static_inst.hh" #include "sim/annotation.hh" +#include "sim/serialize.hh" #include "sim/sim_events.hh" +#include "sim/sim_stats.hh" #ifdef FULL_SYSTEM #include "targetarch/ev5.hh" @@ -2431,20 +2433,58 @@ decode OPCODE default Unknown::unknown() { }}, No_OpClass); 0x21: m5exit({{ if (!xc->misspeculating()) { - Tick when = curTick; Tick delay = xc->regs.intRegFile[16]; - if (delay != 0) { - delay *= ticksPerUS; - delay /= 1000; - when += delay; - } + Tick when = curTick + NS2Ticks(delay); SimExit(when, "m5_exit instruction encountered"); } }}, No_OpClass); 0x30: initparam({{ Ra = xc->cpu->system->init_param; }}); 0x40: resetstats({{ - if (!xc->misspeculating()) - Statistics::reset(); + if (!xc->misspeculating()) { + using namespace Statistics; + Tick delay = xc->regs.intRegFile[16]; + Tick period = xc->regs.intRegFile[17]; + + Tick when = curTick + NS2Ticks(delay); + Tick repeat = NS2Ticks(period); + + SetupEvent(Reset, when, repeat); + } + }}); + 0x41: dumpstats({{ + if (!xc->misspeculating()) { + using namespace Statistics; + Tick delay = xc->regs.intRegFile[16]; + Tick period = xc->regs.intRegFile[17]; + + Tick when = curTick + NS2Ticks(delay); + Tick repeat = NS2Ticks(period); + + SetupEvent(Dump, when, repeat); + } + }}); + 0x42: dumpresetstats({{ + if (!xc->misspeculating()) { + using namespace Statistics; + Tick delay = xc->regs.intRegFile[16]; + Tick period = xc->regs.intRegFile[17]; + + Tick when = curTick + NS2Ticks(delay); + Tick repeat = NS2Ticks(period); + + SetupEvent(Dump|Reset, when, repeat); + } + }}); + 0x43: m5checkpoint({{ + if (!xc->misspeculating()) { + Tick delay = xc->regs.intRegFile[16]; + Tick period = xc->regs.intRegFile[17]; + + Tick when = curTick + NS2Ticks(delay); + Tick repeat = NS2Ticks(period); + + SetupCheckpoint(when, repeat); + } }}); } } -- cgit v1.2.3 From d76445f9f37896227f1d4e61348a418aa7ab6371 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 2 Nov 2003 20:43:39 -0500 Subject: Move the m5 pseudo instructions into their own file arch/alpha/isa_desc: Move the pseudo instructions out of the isa_desc, into their own file and call out to them when they're to be accessed sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: move SimExit to sim_exit.cc --HG-- extra : convert_revision : 1c393adb1c18bd0fef065057d7f4e9cf60ac4197 --- arch/alpha/isa_desc | 63 ++++++++++++----------------------------------------- 1 file changed, 14 insertions(+), 49 deletions(-) (limited to 'arch/alpha/isa_desc') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index e34739b86..ec9fd183a 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -28,12 +28,11 @@ let {{ #include "cpu/simple_cpu/simple_cpu.hh" #include "cpu/static_inst.hh" #include "sim/annotation.hh" -#include "sim/serialize.hh" -#include "sim/sim_events.hh" -#include "sim/sim_stats.hh" +#include "sim/sim_exit.hh" #ifdef FULL_SYSTEM -#include "targetarch/ev5.hh" +#include "arch/alpha/ev5.hh" +#include "arch/alpha/pseudo_inst.hh" #endif namespace AlphaISA; @@ -2429,62 +2428,28 @@ decode OPCODE default Unknown::unknown() { }}, No_OpClass); 0x20: m5exit_old({{ if (!xc->misspeculating()) - SimExit(curTick, "m5_exit_old instruction encountered"); + AlphaPseudo::m5exit_old(xc); }}, No_OpClass); 0x21: m5exit({{ - if (!xc->misspeculating()) { - Tick delay = xc->regs.intRegFile[16]; - Tick when = curTick + NS2Ticks(delay); - SimExit(when, "m5_exit instruction encountered"); - } + if (!xc->misspeculating()) + AlphaPseudo::m5exit(xc); }}, No_OpClass); 0x30: initparam({{ Ra = xc->cpu->system->init_param; }}); 0x40: resetstats({{ - if (!xc->misspeculating()) { - using namespace Statistics; - Tick delay = xc->regs.intRegFile[16]; - Tick period = xc->regs.intRegFile[17]; - - Tick when = curTick + NS2Ticks(delay); - Tick repeat = NS2Ticks(period); - - SetupEvent(Reset, when, repeat); - } + if (!xc->misspeculating()) + AlphaPseudo::resetstats(xc); }}); 0x41: dumpstats({{ - if (!xc->misspeculating()) { - using namespace Statistics; - Tick delay = xc->regs.intRegFile[16]; - Tick period = xc->regs.intRegFile[17]; - - Tick when = curTick + NS2Ticks(delay); - Tick repeat = NS2Ticks(period); - - SetupEvent(Dump, when, repeat); - } + if (!xc->misspeculating()) + AlphaPseudo::dumpstats(xc); }}); 0x42: dumpresetstats({{ - if (!xc->misspeculating()) { - using namespace Statistics; - Tick delay = xc->regs.intRegFile[16]; - Tick period = xc->regs.intRegFile[17]; - - Tick when = curTick + NS2Ticks(delay); - Tick repeat = NS2Ticks(period); - - SetupEvent(Dump|Reset, when, repeat); - } + if (!xc->misspeculating()) + AlphaPseudo::dumpresetstats(xc); }}); 0x43: m5checkpoint({{ - if (!xc->misspeculating()) { - Tick delay = xc->regs.intRegFile[16]; - Tick period = xc->regs.intRegFile[17]; - - Tick when = curTick + NS2Ticks(delay); - Tick repeat = NS2Ticks(period); - - SetupCheckpoint(when, repeat); - } + if (!xc->misspeculating()) + AlphaPseudo::m5checkpoint(xc); }}); } } -- cgit v1.2.3 From c55e6b495e569e2b908ab4f58c3ecb529c64f288 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 3 Nov 2003 16:47:08 -0500 Subject: Make it so the quiesce instruction is conditionally enabled arch/alpha/isa_desc: move the quiesce instruction out of here so I can conditionally enable it. arch/alpha/pseudo_inst.cc: conditionally enable quiesce arch/alpha/pseudo_inst.hh: add quiesce --HG-- extra : convert_revision : e1c474c4bf8761ff58073785d82b2bec9f632885 --- arch/alpha/isa_desc | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/alpha/isa_desc') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index ec9fd183a..4364bae34 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2410,11 +2410,8 @@ decode OPCODE default Unknown::unknown() { } }}); 0x01: quiesce({{ - if (!xc->misspeculating()) { - Annotate::QUIESCE(xc); - xc->setStatus(ExecContext::Suspended); - xc->kernelStats.quiesce(); - } + if (!xc->misspeculating()) + AlphaPseudo::quiesce(xc); }}); 0x10: ivlb({{ if (!xc->misspeculating()) { -- cgit v1.2.3