From 2ad1db3fde4f95eaf0b1be77910de0feb2185712 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 29 Mar 2006 18:42:53 -0500
Subject: page_table.cc is a syscall only kinda thing fix tlbs for newmem

SConscript:
    page_table.cc is a syscall only kinda thing
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
    fix tlbs for newmem

--HG--
extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
---
 arch/alpha/tlb.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch/alpha/tlb.cc')

diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc
index 562235ef8..3f991b10c 100644
--- a/arch/alpha/tlb.cc
+++ b/arch/alpha/tlb.cc
@@ -94,7 +94,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const
 
 
 void
-AlphaTLB::checkCacheability(MemReqPtr &req)
+AlphaTLB::checkCacheability(CpuRequestPtr &req)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -292,7 +292,7 @@ AlphaITB::regStats()
 
 
 Fault
-AlphaITB::translate(MemReqPtr &req) const
+AlphaITB::translate(CpuRequestPtr &req) const
 {
     ExecContext *xc = req->xc;
 
@@ -451,7 +451,7 @@ AlphaDTB::regStats()
 }
 
 Fault
-AlphaDTB::translate(MemReqPtr &req, bool write) const
+AlphaDTB::translate(CpuRequestPtr &req, bool write) const
 {
     ExecContext *xc = req->xc;
     Addr pc = xc->readPC();
-- 
cgit v1.2.3