From 58c29640b7f9ab9f4d1724b6f2c432c2146175f2 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Tue, 1 Mar 2005 00:39:57 -0500
Subject: Add a new operation class for IPR accesses, and have IPR-accessing
 instructions use it (instead of IntALU, as before).  Default config has a
 single non-pipelined 3-cycle unit.  A bit conservative for the ev6 (some are
 1, some are 3).

arch/alpha/isa_desc:
    Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
    Add IprAccess.

--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
---
 arch/alpha/isa_desc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'arch/alpha')

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 5308efaae..6a6bca4fe 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1610,7 +1610,8 @@ output decoder {{
 }};
 
 def format HwMoveIPR(code) {{
-    iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
+    iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
+			['IprAccessOp'])
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
-- 
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