From 5a1eb9049d16d37448282362529d462d73558181 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Wed, 29 Oct 2003 21:45:39 -0800
Subject: Support for Serializable non-SimObject things like events. Can now
 serialize & unserialize DmaRequestEvents and DmaTransferEvents. Also support
 serialize/unserialize of pointers to SimObjects and other Serializable
 objects.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
cpu/simple_cpu/simple_cpu.cc:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
    Put ExecContext in its own section so its _status fields doesn't conflict.
sim/eventq.cc:
sim/eventq.hh:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
    Events get serialized by the event queue only if they're marked
    as AutoSerialize... others are assumed to be serialized by something
    else (e.g. an owning SimObject) or to not matter.
sim/param.cc:
    Shift 'const' in case T is a ptr type.
sim/serialize.cc:
sim/serialize.hh:
    Define Checkpoint object to encapsulate everything you need to know
    about a checkpoint.  Use it to allow lookups of named Serializable
    objects (and SimObjects) during unserialization.
    unserialize() now takes a Checkpoint* instead of an IniFile*.

--HG--
extra : convert_revision : 8e6baab32405f8f548bb67a097b2f713296537a5
---
 arch/alpha/alpha_memory.cc | 4 ++--
 arch/alpha/alpha_memory.hh | 2 +-
 arch/alpha/isa_traits.hh   | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'arch/alpha')

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 7c0b1120f..c79b821d0 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -204,13 +204,13 @@ AlphaTlb::serialize(ostream &os)
 }
 
 void
-AlphaTlb::unserialize(const IniFile *db, const string &section)
+AlphaTlb::unserialize(Checkpoint *cp, const string &section)
 {
     UNSERIALIZE_SCALAR(size);
     UNSERIALIZE_SCALAR(nlu);
 
     for (int i = 0; i < size; i++) {
-        table[i].unserialize(db, csprintf("%s.PTE%d", section, i));
+        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
         if (table[i].valid) {
             lookupTable.insert(make_pair(table[i].tag, i));
         }
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index fc4d46191..bfcd313e2 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -74,7 +74,7 @@ class AlphaTlb : public SimObject
 
     // Checkpointing
     virtual void serialize(std::ostream &os);
-    virtual void unserialize(const IniFile *db, const std::string &section);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
 };
 
 class AlphaItb : public AlphaTlb
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index fbdcffbcf..406ffb6f3 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -34,7 +34,7 @@
 #include "base/misc.hh"
 
 class FullCPU;
-class IniFile;
+class Checkpoint;
 
 #define TARGET_ALPHA
 
@@ -160,7 +160,7 @@ class AlphaISA
         uint8_t opcode, ra;		// current instruction details (for intr's)
 
         void serialize(std::ostream &os);
-        void unserialize(const IniFile *db, const std::string &section);
+        void unserialize(Checkpoint *cp, const std::string &section);
     };
 
     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
-- 
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