From c13ea339dccf54261f753424ff9eb516d97b34a1 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 23 Feb 2006 08:16:59 -0500 Subject: Add pipe() syscall to Alpha Linux emulation. arch/alpha/alpha_linux_process.cc: Add pipeFunc. --HG-- extra : convert_revision : c094d2dff993d5e60bc43b7cd4b9586c15c634a3 --- arch/alpha/alpha_linux_process.cc | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'arch/alpha') diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc index 783b189cc..16ebcca7b 100644 --- a/arch/alpha/alpha_linux_process.cc +++ b/arch/alpha/alpha_linux_process.cc @@ -41,6 +41,31 @@ using namespace std; using namespace AlphaISA; +/// Target pipe() handler. Even though this is a generic Posix call, +/// the Alpha return convention is funky, so that makes it +/// Alpha-specific. +SyscallReturn +pipeFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + int fds[2], sim_fds[2]; + int pipe_retval = pipe(fds); + + if (pipe_retval < 0) { + // error + return pipe_retval; + } + + sim_fds[0] = process->alloc_fd(fds[0]); + sim_fds[1] = process->alloc_fd(fds[1]); + + // Alpha Linux convention for pipe() is that fd[0] is returned as + // the return value of the function, and fd[1] is returned in r20. + xc->regs.intRegFile[20] = sim_fds[1]; + return sim_fds[0]; +} + + /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, @@ -159,7 +184,7 @@ SyscallDesc AlphaLinuxProcess::syscallDescs[] = { /* 39 */ SyscallDesc("setpgid", unimplementedFunc), /* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc), /* 41 */ SyscallDesc("dup", unimplementedFunc), - /* 42 */ SyscallDesc("pipe", unimplementedFunc), + /* 42 */ SyscallDesc("pipe", pipeFunc), /* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc), /* 44 */ SyscallDesc("osf_profil", unimplementedFunc), /* 45 */ SyscallDesc("open", openFunc), -- cgit v1.2.3 From 99484cfae81f3f01ccdfcd273ddc2bdb41e6456b Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 23 Feb 2006 14:31:15 -0500 Subject: Create a Builder object for .isa files in arch/SConscript. Start using SCons File objects to avoid fixed paths in subordinate SConscripts. SConscript: Push isa_parser stuff (including .isa scanner) down into arch/SConscript. arch/SConscript: Create a Builder object for .isa files, including existing scanner. Return file objects generated by isa-specific SConscript back up to parent. arch/alpha/SConscript: arch/mips/SConscript: arch/sparc/SConscript: Convert sources to scons File objects, so file names can be specified relative to the current directory. Invoke new builder for isa description, and get generated sources from there (instead of listing them explicitly). arch/isa_parser.py: Get rid of third argument ("include_path"). It was a pain to generate this from scons, and it turned out it's not needed anyway, since the only included file (decoder.hh) will be in the same directory as the sources. --HG-- extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581 --- arch/alpha/SConscript | 49 +++++++++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 22 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript index a5ae77dac..050dfb9cf 100644 --- a/arch/alpha/SConscript +++ b/arch/alpha/SConscript @@ -43,40 +43,45 @@ Import('env') ################################################### # Base sources used by all configurations. -arch_base_sources = Split(''' - arch/alpha/decoder.cc - arch/alpha/alpha_o3_exec.cc - arch/alpha/fast_cpu_exec.cc - arch/alpha/simple_cpu_exec.cc - arch/alpha/full_cpu_exec.cc - arch/alpha/faults.cc - arch/alpha/isa_traits.cc +base_sources = Split(''' + faults.cc + isa_traits.cc ''') # Full-system sources -arch_full_system_sources = Split(''' - arch/alpha/alpha_memory.cc - arch/alpha/arguments.cc - arch/alpha/ev5.cc - arch/alpha/osfpal.cc - arch/alpha/stacktrace.cc - arch/alpha/vtophys.cc +full_system_sources = Split(''' + alpha_memory.cc + arguments.cc + ev5.cc + osfpal.cc + stacktrace.cc + vtophys.cc ''') # Syscall emulation (non-full-system) sources -arch_syscall_emulation_sources = Split(''' - arch/alpha/alpha_common_syscall_emul.cc - arch/alpha/alpha_linux_process.cc - arch/alpha/alpha_tru64_process.cc +syscall_emulation_sources = Split(''' + alpha_common_syscall_emul.cc + alpha_linux_process.cc + alpha_tru64_process.cc ''') # Set up complete list of sources based on configuration. -sources = arch_base_sources +sources = base_sources if env['FULL_SYSTEM']: - sources += arch_full_system_sources + sources += full_system_sources else: - sources += arch_syscall_emulation_sources + sources += syscall_emulation_sources + +# Convert file names to SCons File objects. This takes care of the +# path relative to the top of the directory tree. +sources = [File(s) for s in sources] + +# Add in files generated by the ISA description. +isa_desc_files = env.ISADesc('isa/main.isa') +# Only non-header files need to be compiled. +isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')] +sources += isa_desc_sources Return('sources') -- cgit v1.2.3 From 1166d4f0bfe67a9dc178be3454b4f0eac38663ad Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 23 Feb 2006 14:50:16 -0500 Subject: Get rid of the xc from the alphaAccess/alphaConsole backdoor device. Now allocate an array of stacks indexed by cpu number which specify cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for their stacks before continuing. This change *REQUIRES* a the new console code to operate correctly. arch/alpha/ev5.cc: Add cpuId to initCPU/initIPR functions cpu/o3/cpu.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move the cpu initilization into an init() function since it now needs the CPU id which isn't known at construction dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: instead of the bootstrap variables, add space for 64 cpu stacks in the alpha access structure. sim/system.cc: start all cpus immediately rather than just the first one --HG-- extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b --- arch/alpha/ev5.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 125affd03..bd076dae4 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -70,12 +70,15 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) // Machine dependent functions // void -AlphaISA::initCPU(RegFile *regs) +AlphaISA::initCPU(RegFile *regs, int cpuId) { - initIPRs(regs); + initIPRs(regs, cpuId); // CPU comes up with PAL regs enabled swap_palshadow(regs, true); + regs->intRegFile[16] = cpuId; + regs->intRegFile[0] = cpuId; + regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault]; regs->npc = regs->pc + sizeof(MachInst); } @@ -116,13 +119,14 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { // // void -AlphaISA::initIPRs(RegFile *regs) +AlphaISA::initIPRs(RegFile *regs, int cpuId) { uint64_t *ipr = regs->ipr; bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); ipr[IPR_PAL_BASE] = PalBase; ipr[IPR_MCSR] = 0x6; + ipr[IPR_PALtemp16] = cpuId; } -- cgit v1.2.3 From 4f831bc5610abfdb94ddfed9af5f1398182ff0b4 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 23 Feb 2006 15:08:08 -0500 Subject: ev5.cc: SCCS merged arch/alpha/ev5.cc: SCCS merged --HG-- extra : convert_revision : 9d70c1d461dab0ec016fd0616d74a49942aac659 --- arch/alpha/ev5.cc | 70 ++++++++++++++++++++++++------------------------------- 1 file changed, 30 insertions(+), 40 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index bd076dae4..14b87b16f 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -79,7 +79,7 @@ AlphaISA::initCPU(RegFile *regs, int cpuId) regs->intRegFile[16] = cpuId; regs->intRegFile[0] = cpuId; - regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault]; + regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault); regs->npc = regs->pc + sizeof(MachInst); } @@ -87,25 +87,15 @@ AlphaISA::initCPU(RegFile *regs, int cpuId) // // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE // -Addr -AlphaISA::fault_addr[Num_Faults] = { - 0x0000, /* No_Fault */ - 0x0001, /* Reset_Fault */ - 0x0401, /* Machine_Check_Fault */ - 0x0501, /* Arithmetic_Fault */ - 0x0101, /* Interrupt_Fault */ - 0x0201, /* Ndtb_Miss_Fault */ - 0x0281, /* Pdtb_Miss_Fault */ - 0x0301, /* Alignment_Fault */ - 0x0381, /* DTB_Fault_Fault */ - 0x0381, /* DTB_Acv_Fault */ - 0x0181, /* ITB_Miss_Fault */ - 0x0181, /* ITB_Fault_Fault */ - 0x0081, /* ITB_Acv_Fault */ - 0x0481, /* Unimplemented_Opcode_Fault */ - 0x0581, /* Fen_Fault */ - 0x2001, /* Pal_Fault */ - 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */ +const Addr +AlphaISA::fault_addr(Fault fault) +{ + //Check for the system wide faults + if(fault == NoFault) return 0x0000; + else if(fault == MachineCheckFault) return 0x0401; + else if(fault == AlignmentFault) return 0x0301; + //Deal with the alpha specific faults + return ((AlphaFault*)fault)->vect; }; const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { @@ -172,7 +162,7 @@ AlphaISA::processInterrupts(CPU *cpu) if (ipl && ipl > ipr[IPR_IPLR]) { ipr[IPR_ISR] = summary; ipr[IPR_INTID] = ipl; - cpu->trap(Interrupt_Fault); + cpu->trap(InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[IPR_IPLR], ipl, summary); } @@ -193,23 +183,23 @@ AlphaISA::zeroRegisters(CPU *cpu) void ExecContext::ev5_trap(Fault fault) { - DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc); - cpu->recordEvent(csprintf("Fault %s", FaultName(fault))); + DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc); + cpu->recordEvent(csprintf("Fault %s", fault->name)); assert(!misspeculating()); kernelStats->fault(fault); - if (fault == Arithmetic_Fault) + if (fault == ArithmeticFault) panic("Arithmetic traps are unimplemented!"); AlphaISA::InternalProcReg *ipr = regs.ipr; // exception restart address - if (fault != Interrupt_Fault || !inPalMode()) + if (fault != InterruptFault || !inPalMode()) ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc; - if (fault == Pal_Fault || fault == Arithmetic_Fault /* || - fault == Interrupt_Fault && !inPalMode() */) { + if (fault == PalFault || fault == ArithmeticFault /* || + fault == InterruptFault && !inPalMode() */) { // traps... skip faulting instruction ipr[AlphaISA::IPR_EXC_ADDR] += 4; } @@ -217,7 +207,7 @@ ExecContext::ev5_trap(Fault fault) if (!inPalMode()) AlphaISA::swap_palshadow(®s, true); - regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault]; + regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault); regs.npc = regs.pc + sizeof(MachInst); } @@ -226,13 +216,13 @@ void AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) { InternalProcReg *ipr = regs->ipr; - bool use_pc = (fault == No_Fault); + bool use_pc = (fault == NoFault); - if (fault == Arithmetic_Fault) + if (fault == ArithmeticFault) panic("arithmetic faults NYI..."); // compute exception restart address - if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) { + if (use_pc || fault == PalFault || fault == ArithmeticFault) { // traps... skip faulting instruction ipr[IPR_EXC_ADDR] = regs->pc + 4; } else { @@ -242,7 +232,7 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) // jump to expection address (PAL PC bit set here as well...) if (!use_pc) - regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault]; + regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault); else regs->npc = ipr[IPR_PAL_BASE] + pc; @@ -255,7 +245,7 @@ ExecContext::hwrei() uint64_t *ipr = regs.ipr; if (!inPalMode()) - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); @@ -269,7 +259,7 @@ ExecContext::hwrei() } // FIXME: XXX check for interrupts? XXX - return No_Fault; + return NoFault; } uint64_t @@ -367,12 +357,12 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_DTB_IAP: case AlphaISA::IPR_ITB_IA: case AlphaISA::IPR_ITB_IAP: - fault = Unimplemented_Opcode_Fault; + fault = UnimplementedOpcodeFault; break; default: // invalid IPR - fault = Unimplemented_Opcode_Fault; + fault = UnimplementedOpcodeFault; break; } @@ -391,7 +381,7 @@ ExecContext::setIpr(int idx, uint64_t val) uint64_t old; if (misspeculating()) - return No_Fault; + return NoFault; switch (idx) { case AlphaISA::IPR_PALtemp0: @@ -537,7 +527,7 @@ ExecContext::setIpr(int idx, uint64_t val) case AlphaISA::IPR_ITB_PTE_TEMP: case AlphaISA::IPR_DTB_PTE_TEMP: // read-only registers - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; case AlphaISA::IPR_HWINT_CLR: case AlphaISA::IPR_SL_XMIT: @@ -639,11 +629,11 @@ ExecContext::setIpr(int idx, uint64_t val) default: // invalid IPR - return Unimplemented_Opcode_Fault; + return UnimplementedOpcodeFault; } // no error... - return No_Fault; + return NoFault; } /** -- cgit v1.2.3