From 7b07b0877f05cffa93b782a76a15791c1126216a Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Mon, 2 Feb 2004 10:47:21 -0800
Subject: Change MemReqPtr parameters to references. This avoids incrementing
 and decrementing the MemReq reference counters on every call and return.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
    Change MemReqPtr parameters to references.

--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
---
 arch/alpha/alpha_memory.cc | 6 +++---
 arch/alpha/alpha_memory.hh | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'arch/alpha')

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index d934299b8..0f9ad2cfc 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const
 
 
 void
-AlphaTlb::checkCacheability(MemReqPtr req)
+AlphaTlb::checkCacheability(MemReqPtr &req)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -260,7 +260,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const
 
 
 Fault
-AlphaItb::translate(MemReqPtr req) const
+AlphaItb::translate(MemReqPtr &req) const
 {
     InternalProcReg *ipr = req->xc->regs.ipr;
 
@@ -425,7 +425,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
 }
 
 Fault
-AlphaDtb::translate(MemReqPtr req, bool write) const
+AlphaDtb::translate(MemReqPtr &req, bool write) const
 {
     RegFile *regs = &req->xc->regs;
     Addr pc = regs->pc;
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index bfcd313e2..482a13eee 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -70,7 +70,7 @@ class AlphaTlb : public SimObject
         return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
     }
 
-    static void checkCacheability(MemReqPtr req);
+    static void checkCacheability(MemReqPtr &req);
 
     // Checkpointing
     virtual void serialize(std::ostream &os);
@@ -92,7 +92,7 @@ class AlphaItb : public AlphaTlb
     AlphaItb(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req) const;
+    Fault translate(MemReqPtr &req) const;
 };
 
 class AlphaDtb : public AlphaTlb
@@ -118,7 +118,7 @@ class AlphaDtb : public AlphaTlb
     AlphaDtb(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req, bool write) const;
+    Fault translate(MemReqPtr &req, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__
-- 
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