From 2ad1db3fde4f95eaf0b1be77910de0feb2185712 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 29 Mar 2006 18:42:53 -0500 Subject: page_table.cc is a syscall only kinda thing fix tlbs for newmem SConscript: page_table.cc is a syscall only kinda thing arch/alpha/tlb.cc: arch/alpha/tlb.hh: fix tlbs for newmem --HG-- extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408 --- arch/alpha/tlb.cc | 6 +++--- arch/alpha/tlb.hh | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc index 562235ef8..3f991b10c 100644 --- a/arch/alpha/tlb.cc +++ b/arch/alpha/tlb.cc @@ -94,7 +94,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const void -AlphaTLB::checkCacheability(MemReqPtr &req) +AlphaTLB::checkCacheability(CpuRequestPtr &req) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address @@ -292,7 +292,7 @@ AlphaITB::regStats() Fault -AlphaITB::translate(MemReqPtr &req) const +AlphaITB::translate(CpuRequestPtr &req) const { ExecContext *xc = req->xc; @@ -451,7 +451,7 @@ AlphaDTB::regStats() } Fault -AlphaDTB::translate(MemReqPtr &req, bool write) const +AlphaDTB::translate(CpuRequestPtr &req, bool write) const { ExecContext *xc = req->xc; Addr pc = xc->readPC(); diff --git a/arch/alpha/tlb.hh b/arch/alpha/tlb.hh index 676345f01..fe156b7e3 100644 --- a/arch/alpha/tlb.hh +++ b/arch/alpha/tlb.hh @@ -35,7 +35,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/faults.hh" #include "base/statistics.hh" -#include "mem/mem_req.hh" +#include "mem/request.hh" #include "sim/sim_object.hh" class ExecContext; @@ -73,7 +73,7 @@ class AlphaTLB : public SimObject return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); } - static void checkCacheability(MemReqPtr &req); + static void checkCacheability(CpuRequestPtr &req); // Checkpointing virtual void serialize(std::ostream &os); @@ -92,7 +92,7 @@ class AlphaITB : public AlphaTLB AlphaITB(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr &req) const; + Fault translate(CpuRequestPtr &req) const; }; class AlphaDTB : public AlphaTLB @@ -115,7 +115,7 @@ class AlphaDTB : public AlphaTLB AlphaDTB(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr &req, bool write) const; + Fault translate(CpuRequestPtr &req, bool write) const; }; #endif // __ALPHA_MEMORY_HH__ -- cgit v1.2.3 From 0b2deb2a8897fa857d2b3e1936401c6666fdc728 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 30 Mar 2006 10:42:55 -0500 Subject: Fixes for full system compiling. arch/alpha/arguments.cc: There will not be a phys mem ptr in the XC in the newmem. This read will have to go through something else. arch/alpha/ev5.cc: Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used. Also this messed up the ability to specify which CPU models are being built. cpu/exec_context.hh: Remove getPhysMemPtr() function. cpu/exetrace.cc: Include sim/system.hh, and sort the includes. cpu/simple/cpu.cc: Fixes for full system compilation. kern/system_events.cc: Remove include of encumbered FullCPU. The branch prediction will need to be fixed up in a more generic way in the future. --HG-- extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c --- arch/alpha/arguments.cc | 4 +++- arch/alpha/ev5.cc | 9 --------- 2 files changed, 3 insertions(+), 10 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc index a782ea330..338581e32 100644 --- a/arch/alpha/arguments.cc +++ b/arch/alpha/arguments.cc @@ -60,7 +60,9 @@ AlphaArguments::getArg(bool fp) } else { Addr sp = xc->readIntReg(30); Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t)); - return xc->getPhysMemPtr()->phys_read_qword(paddr); + // @todo: This read must go through the system or something else. +// return xc->getPhysMemPtr()->phys_read_qword(paddr); + return 0; } } diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index a5a8851c2..12f7659e6 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -36,7 +36,6 @@ #include "cpu/base.hh" #include "cpu/cpu_exec_context.hh" #include "cpu/exec_context.hh" -#include "cpu/fast/cpu.hh" #include "kern/kernel_stats.hh" #include "sim/debug.hh" #include "sim/sim_events.hh" @@ -575,12 +574,4 @@ CPUExecContext::simPalCheck(int palFunc) return true; } -//Forward instantiation for FastCPU object -template -void AlphaISA::processInterrupts(FastCPU *xc); - -//Forward instantiation for FastCPU object -template -void AlphaISA::zeroRegisters(FastCPU *xc); - #endif // FULL_SYSTEM -- cgit v1.2.3 From e196d20d9d047a869e1d853fd02077b1d909a576 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 30 Mar 2006 15:59:49 -0500 Subject: Make TranslatingPort be a type of Port rather than something special arch/alpha/arguments.cc: rather than returning 0, put a panic in... it will actually make us fix this rather than scratching our respective heads base/loader/object_file.cc: base/loader/object_file.hh: Object loader now takes a port rather than a translating port cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: sim/process.cc: Make translating port a type of port rather than anything special cpu/simple/cpu.cc: no need to grab a port from the cpu anymore mem/physical.cc: add an additional type of port to physicalmemory called "functional" Only used for functional accesses (loading binaries/syscall emu) mem/port.hh: make readBlok/writeBlob virtual so translating port can do the translation first mem/translating_port.cc: mem/translating_port.hh: Make TranslatingPort inherit from Port sim/system.cc: header file that doesn't exit removed --HG-- extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7 --- arch/alpha/arguments.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/alpha') diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc index 338581e32..fe6e78abc 100644 --- a/arch/alpha/arguments.cc +++ b/arch/alpha/arguments.cc @@ -62,6 +62,7 @@ AlphaArguments::getArg(bool fp) Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t)); // @todo: This read must go through the system or something else. // return xc->getPhysMemPtr()->phys_read_qword(paddr); + panic("Need to fix alpha arguments\n"); return 0; } } -- cgit v1.2.3 From 5936c79ba0f3fd29ef2bbf41fcaddc78fcd9c75c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 30 Mar 2006 18:06:00 -0500 Subject: Add a functional port that is used to load the original binaries in FS SE mode now has a port that goes to whatever toplevel mem object the CPU sees that does the appropriate translation for syscall emulation SConscript: translating port is a syscall emu only source arch/alpha/system.cc: base/loader/object_file.cc: base/loader/object_file.hh: Use the new functional port to write the binaries into memory cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/simple/cpu.cc: We aren't always going to be writing straight to memory with syscalls support writing to a cache mem/port.hh: Add a simple unidirectional functional port that panics on any incoming requests mem/translating_port.hh: make translating port inherit from the simple port sim/system.cc: sim/system.hh: Add a functional port that is used to load the original binaries --HG-- extra : convert_revision : 9096866d0b23e3aceea68394abb76e63c0f8fd8d --- arch/alpha/system.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/system.cc b/arch/alpha/system.cc index 547e89cff..8dfc3cbc4 100644 --- a/arch/alpha/system.cc +++ b/arch/alpha/system.cc @@ -63,8 +63,8 @@ AlphaSystem::AlphaSystem(Params *p) // Load program sections into memory - pal->loadSections(physmem, true); - console->loadSections(physmem, true); + pal->loadSections(&functionalPort, LoadAddrMask); + console->loadSections(&functionalPort, LoadAddrMask); // load symbols if (!console->loadGlobalSymbols(consoleSymtab)) -- cgit v1.2.3