From c4793184bd32e97e8932a9a0355d8a7b8a214752 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 30 Aug 2005 13:18:54 -0400 Subject: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad --- arch/alpha/alpha_memory.cc | 13 +++++++------ arch/alpha/ev5.cc | 3 ++- arch/alpha/ev5.hh | 8 +++++--- arch/alpha/isa_desc | 45 +++++++++++++++++---------------------------- arch/alpha/isa_traits.hh | 9 +++++---- 5 files changed, 36 insertions(+), 42 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 906f60668..39c9397ea 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -34,6 +34,7 @@ #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" +#include "config/alpha_tlaser.hh" #include "cpu/exec_context.hh" #include "sim/builder.hh" @@ -107,7 +108,7 @@ AlphaTLB::checkCacheability(MemReqPtr &req) */ -#ifdef ALPHA_TLASER +#if ALPHA_TLASER if (req->paddr & PAddrUncachedBit39) { #else if (req->paddr & PAddrUncachedBit43) { @@ -129,7 +130,7 @@ AlphaTLB::checkCacheability(MemReqPtr &req) // mark request as uncacheable req->flags |= UNCACHEABLE; -#ifndef ALPHA_TLASER +#if !ALPHA_TLASER // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) req->paddr &= PAddrUncachedMask; #endif @@ -323,7 +324,7 @@ AlphaITB::translate(MemReqPtr &req) const // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 -#ifdef ALPHA_TLASER +#if ALPHA_TLASER if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && VAddrSpaceEV5(req->vaddr) == 2) { #else @@ -339,7 +340,7 @@ AlphaITB::translate(MemReqPtr &req) const req->paddr = req->vaddr & PAddrImplMask; -#ifndef ALPHA_TLASER +#if !ALPHA_TLASER // sign extend the physical address properly if (req->paddr & PAddrUncachedBit40) req->paddr |= ULL(0xf0000000000); @@ -529,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const } // Check for "superpage" mapping -#ifdef ALPHA_TLASER +#if ALPHA_TLASER if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && VAddrSpaceEV5(req->vaddr) == 2) { #else @@ -547,7 +548,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const req->paddr = req->vaddr & PAddrImplMask; -#ifndef ALPHA_TLASER +#if !ALPHA_TLASER // sign extend the physical address properly if (req->paddr & PAddrUncachedBit40) req->paddr |= ULL(0xf0000000000); diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 4ae688330..125affd03 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -32,6 +32,7 @@ #include "base/kgdb.h" #include "base/remote_gdb.hh" #include "base/stats/events.hh" +#include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/exec_context.hh" #include "cpu/fast/cpu.hh" @@ -39,7 +40,7 @@ #include "sim/debug.hh" #include "sim/sim_events.hh" -#ifdef FULL_SYSTEM +#if FULL_SYSTEM using namespace EV5; diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh index a5a76b5bd..5173b364f 100644 --- a/arch/alpha/ev5.hh +++ b/arch/alpha/ev5.hh @@ -29,9 +29,11 @@ #ifndef __ARCH_ALPHA_EV5_HH__ #define __ARCH_ALPHA_EV5_HH__ +#include "config/alpha_tlaser.hh" + namespace EV5 { -#ifdef ALPHA_TLASER +#if ALPHA_TLASER const uint64_t AsnMask = ULL(0x7f); #else const uint64_t AsnMask = ULL(0xff); @@ -46,7 +48,7 @@ inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } -#ifdef ALPHA_TLASER +#if ALPHA_TLASER inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } const int PAddrImplBits = 40; #else @@ -60,7 +62,7 @@ const Addr PAddrUncachedBit43 = ULL(0x80000000000); const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> inline Addr Phys2K0Seg(Addr addr) { -#ifndef ALPHA_TLASER +#if !ALPHA_TLASER if (addr & PAddrUncachedBit43) { addr &= PAddrUncachedMask; addr |= PAddrUncachedBit40; diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 12b2a4822..60ffbfd54 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -45,30 +45,29 @@ output header {{ #include #include +#include "config/ss_compatible_fp.hh" #include "cpu/static_inst.hh" #include "mem/mem_req.hh" // some constructors use MemReq flags }}; output decoder {{ #include "base/cprintf.hh" +#include "base/fenv.hh" #include "base/loader/symtab.hh" +#include "config/ss_compatible_fp.hh" #include "cpu/exec_context.hh" // for Jump::branchTarget() #include -#if defined(linux) -#include -#endif }}; output exec {{ #include -#if defined(linux) -#include -#endif -#ifdef FULL_SYSTEM +#if FULL_SYSTEM #include "arch/alpha/pseudo_inst.hh" #endif +#include "base/fenv.hh" +#include "config/ss_compatible_fp.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" #include "sim/sim_exit.hh" @@ -542,7 +541,7 @@ output exec {{ /// instruction in full-system mode. /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault /// if not. Non-full-system mode: always returns No_Fault. -#ifdef FULL_SYSTEM +#if FULL_SYSTEM inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) { Fault fault = No_Fault; // dummy... this ipr access should not fault @@ -593,9 +592,8 @@ output header {{ }; protected: -#if defined(linux) + /// Map Alpha rounding mode to C99 constants from . static const int alphaToC99RoundingMode[]; -#endif /// Map enum RoundingMode values to disassembly suffixes. static const char *roundingModeSuffix[]; @@ -620,9 +618,7 @@ output header {{ } } -#if defined(linux) int getC99RoundingMode(uint64_t fpcr_val) const; -#endif // This differs from the AlphaStaticInst version only in // printing suffixes for non-default rounding & trapping modes. @@ -650,7 +646,6 @@ def template FloatingPointDecode {{ }}; output decoder {{ -#if defined(linux) int AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const { @@ -661,7 +656,6 @@ output decoder {{ return alphaToC99RoundingMode[roundingMode]; } } -#endif std::string AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const @@ -705,14 +699,12 @@ output decoder {{ return ss.str(); } -#if defined(linux) const int AlphaFP::alphaToC99RoundingMode[] = { FE_TOWARDZERO, // Chopped FE_DOWNWARD, // Minus_Infinity FE_TONEAREST, // Normal FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR }; -#endif const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" }; // mark invalid trapping modes, but don't fail on them, because @@ -738,14 +730,11 @@ def format FloatingPointOperate(code, *opt_args) {{ exec_output = BasicExecute.subst(fast_iop) gen_code_prefix = r''' -#if defined(linux) fesetround(getC99RoundingMode(xc->readFpcr())); -#endif ''' + gen_code_suffix = r''' -#if defined(linux) fesetround(FE_TONEAREST); -#endif ''' gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP', @@ -2080,7 +2069,7 @@ decode OPCODE default Unknown::unknown() { 1: decode INTIMM { // return EV5 for FULL_SYSTEM and EV6 otherwise 1: implver({{ -#ifdef FULL_SYSTEM +#if FULL_SYSTEM Rc = 1; #else Rc = 2; @@ -2090,7 +2079,7 @@ decode OPCODE default Unknown::unknown() { } } -#ifdef FULL_SYSTEM +#if FULL_SYSTEM // The mysterious 11.25... 0x25: WarnUnimpl::eleven25(); #endif @@ -2310,7 +2299,7 @@ decode OPCODE default Unknown::unknown() { 0xb: decode FA { 31: decode FP_TYPEFUNC { format FloatingPointOperate { -#ifdef SS_COMPATIBLE_FP +#if SS_COMPATIBLE_FP 0x0b: sqrts({{ if (Fb < 0.0) fault = Arithmetic_Fault; @@ -2350,7 +2339,7 @@ decode OPCODE default Unknown::unknown() { // and source type. 0: decode FP_TYPEFUNC { format FloatingPointOperate { -#ifdef SS_COMPATIBLE_FP +#if SS_COMPATIBLE_FP 0x00: adds({{ Fc = Fa + Fb; }}); 0x01: subs({{ Fc = Fa - Fb; }}); 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); @@ -2484,7 +2473,7 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0xc000: rpcc({{ -#ifdef FULL_SYSTEM +#if FULL_SYSTEM /* Rb is a fake dependency so here is a fun way to get * the parser to understand that. */ @@ -2517,7 +2506,7 @@ decode OPCODE default Unknown::unknown() { 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); } -#ifdef FULL_SYSTEM +#if FULL_SYSTEM format BasicOperate { 0xe000: rc({{ Ra = xc->readIntrFlag(); @@ -2536,7 +2525,7 @@ decode OPCODE default Unknown::unknown() { #endif } -#ifdef FULL_SYSTEM +#if FULL_SYSTEM 0x00: CallPal::call_pal({{ if (!palValid || (palPriv @@ -2574,7 +2563,7 @@ decode OPCODE default Unknown::unknown() { } #endif -#ifdef FULL_SYSTEM +#if FULL_SYSTEM format HwLoadStore { 0x1b: decode HW_LDST_QUAD { 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 6c0c09b7a..cc6d81478 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -31,6 +31,7 @@ #include "arch/alpha/faults.hh" #include "base/misc.hh" +#include "config/full_system.hh" #include "sim/host.hh" class FastCPU; @@ -131,7 +132,7 @@ static const Addr PageBytes = ULL(1) << PageShift; static const Addr PageMask = ~(PageBytes - 1); static const Addr PageOffset = PageBytes - 1; -#ifdef FULL_SYSTEM +#if FULL_SYSTEM typedef uint64_t InternalProcReg; @@ -164,7 +165,7 @@ static const Addr PageOffset = PageBytes - 1; MiscRegFile miscRegs; // control register file Addr pc; // program counter Addr npc; // next-cycle program counter -#ifdef FULL_SYSTEM +#if FULL_SYSTEM IntReg palregs[NumIntRegs]; // PAL shadow registers InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs int intrflag; // interrupt flag @@ -291,7 +292,7 @@ const int ArgumentReg2 = TheISA::ArgumentReg2; const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; const int MaxAddr = (Addr)-1; -#ifndef FULL_SYSTEM +#if !FULL_SYSTEM class SyscallReturn { public: template @@ -328,7 +329,7 @@ class SyscallReturn { #endif -#ifdef FULL_SYSTEM +#if FULL_SYSTEM typedef TheISA::InternalProcReg InternalProcReg; const int NumInternalProcRegs = TheISA::NumInternalProcRegs; const int NumInterruptLevels = TheISA::NumInterruptLevels; -- cgit v1.2.3