From cbc42f1d71323fa94ad2b5262258c1d6b1c0b0bf Mon Sep 17 00:00:00 2001 From: Erik Hallnor Date: Sun, 29 Feb 2004 22:41:11 -0500 Subject: Remove copys from isa_desc, and implement a store and forward bus bridge arch/alpha/isa_desc: Just to make sure, remove the new copy instructions until everything works. --HG-- extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a --- arch/alpha/isa_desc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 0cfe5b452..a7665210f 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1854,9 +1854,9 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); - 0x20: copy_load({{EA = Ra;}}, - {{memAccessObj->copySrcTranslate(EA);}}, - IsMemRef, IsLoad, IsCopy); + //0x20: copy_load({{EA = Ra;}}, + // {{memAccessObj->copySrcTranslate(EA);}}, + // IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1876,9 +1876,9 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); - 0x24: copy_store({{EA = Rb;}}, - {{memAccessObj->copy(EA);}}, - IsMemRef, IsStore, IsCopy); + //0x24: copy_store({{EA = Rb;}}, + // {{memAccessObj->copy(EA);}}, + // IsMemRef, IsStore, IsCopy); } format StoreCond { -- cgit v1.2.3