From 8e4ec55703305efff059bce2bab0af3eeec561e6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 14 Mar 2006 15:55:00 -0500 Subject: Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. arch/alpha/arguments.cc: Renamed readFloatRegInt to readFloatRegBits arch/alpha/ev5.cc: Removed the Double from setFloatRegDouble arch/alpha/registerfile.hh: Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC. arch/alpha/types.hh: Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register. arch/isa_parser.py: Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg. base/remote_gdb.cc: kern/tru64/tru64.hh: Replaced setFloatRegInt with setFloatRegBits cpu/cpu_exec_context.cc: Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/regfile.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.hh: Implemented the new versions of the floating point read and set functions. cpu/simple/cpu.cc: Replaced setFloatRegDouble with setFloatReg --HG-- extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2 --- arch/alpha/arguments.cc | 2 +- arch/alpha/ev5.cc | 2 +- arch/alpha/registerfile.hh | 66 +++++++++++++++++++++++++++++++++++++++++----- arch/alpha/types.hh | 6 ++--- 4 files changed, 64 insertions(+), 12 deletions(-) (limited to 'arch/alpha') diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc index 019390aeb..a782ea330 100644 --- a/arch/alpha/arguments.cc +++ b/arch/alpha/arguments.cc @@ -54,7 +54,7 @@ AlphaArguments::getArg(bool fp) { if (number < 6) { if (fp) - return xc->readFloatRegInt(16 + number); + return xc->readFloatRegBits(16 + number); else return xc->readIntReg(16 + number); } else { diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 019e83dd4..fed2f5358 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -134,7 +134,7 @@ AlphaISA::zeroRegisters(CPU *cpu) // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) cpu->cpuXC->setIntReg(ZeroReg, 0); - cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0); + cpu->cpuXC->setFloatReg(ZeroReg, 0.0); } Fault diff --git a/arch/alpha/registerfile.hh b/arch/alpha/registerfile.hh index c2fb56ec1..13288e087 100644 --- a/arch/alpha/registerfile.hh +++ b/arch/alpha/registerfile.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __ARCH_ALPHA_REGISTERFILE_HH__ -#define __ARCH_ALPHA_REGISTERFILE_HH__ +#ifndef __ARCH_ALPHA_REGFILE_HH__ +#define __ARCH_ALPHA_REGFILE_HH__ #include "arch/alpha/types.hh" #include "arch/alpha/constants.hh" @@ -40,10 +40,64 @@ namespace AlphaISA typedef IntReg IntRegFile[NumIntRegs]; - typedef union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - } FloatRegFile; + class FloatRegFile + { + protected: + + union { + uint64_t q[NumFloatRegs]; // integer qword view + double d[NumFloatRegs]; // double-precision floating point view + }; + + public: + + FloatReg readReg(int floatReg) + { + return d[floatReg]; + } + + FloatReg readReg(int floatReg, int width) + { + return readReg(floatReg); + } + + FloatRegBits readRegBits(int floatReg) + { + return q[floatReg]; + } + + FloatRegBits readRegBits(int floatReg, int width) + { + return readRegBits(floatReg); + } + + Fault setReg(int floatReg, const FloatReg &val) + { + d[floatReg] = val; + return NoFault; + } + + Fault setReg(int floatReg, const FloatReg &val, int width) + { + return setReg(floatReg, val); + } + + Fault setRegBits(int floatReg, const FloatRegBits &val) + { + q[floatReg] = val; + return NoFault; + } + + Fault setRegBits(int floatReg, const FloatRegBits &val, int width) + { + return setRegBits(floatReg, val); + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + + }; class MiscRegFile { protected: diff --git a/arch/alpha/types.hh b/arch/alpha/types.hh index 7af3bebd8..3cd93c6b0 100644 --- a/arch/alpha/types.hh +++ b/arch/alpha/types.hh @@ -54,10 +54,8 @@ namespace AlphaISA typedef uint64_t IntReg; // floating point register file entry type - typedef union { - uint64_t q; - double d; - } FloatReg; + typedef double FloatReg; + typedef uint64_t FloatRegBits; // control register file contents typedef uint64_t MiscReg; -- cgit v1.2.3 From efe46430fac2419a02062e3b282324498a55df28 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 14 Mar 2006 16:05:44 -0500 Subject: Moved registerfile.hh to regfile.hh --HG-- rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh extra : convert_revision : 27df93cd2259dab85057f966c801c0db2cb6f022 --- arch/alpha/isa_traits.hh | 2 +- arch/alpha/regfile.hh | 164 +++++++++++++++++++++++++++++++++++++++++++++ arch/alpha/registerfile.hh | 164 --------------------------------------------- arch/alpha/utility.hh | 2 +- 4 files changed, 166 insertions(+), 166 deletions(-) create mode 100644 arch/alpha/regfile.hh delete mode 100644 arch/alpha/registerfile.hh (limited to 'arch/alpha') diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 1ab3b989d..5f8b00c40 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -33,7 +33,7 @@ namespace LittleEndianGuest {} #include "arch/alpha/types.hh" #include "arch/alpha/constants.hh" -#include "arch/alpha/registerfile.hh" +#include "arch/alpha/regfile.hh" #include "config/full_system.hh" #include "sim/host.hh" diff --git a/arch/alpha/regfile.hh b/arch/alpha/regfile.hh new file mode 100644 index 000000000..13288e087 --- /dev/null +++ b/arch/alpha/regfile.hh @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ALPHA_REGFILE_HH__ +#define __ARCH_ALPHA_REGFILE_HH__ + +#include "arch/alpha/types.hh" +#include "arch/alpha/constants.hh" +#include "sim/faults.hh" + +class Checkpoint; + +namespace AlphaISA +{ + + typedef IntReg IntRegFile[NumIntRegs]; + + class FloatRegFile + { + protected: + + union { + uint64_t q[NumFloatRegs]; // integer qword view + double d[NumFloatRegs]; // double-precision floating point view + }; + + public: + + FloatReg readReg(int floatReg) + { + return d[floatReg]; + } + + FloatReg readReg(int floatReg, int width) + { + return readReg(floatReg); + } + + FloatRegBits readRegBits(int floatReg) + { + return q[floatReg]; + } + + FloatRegBits readRegBits(int floatReg, int width) + { + return readRegBits(floatReg); + } + + Fault setReg(int floatReg, const FloatReg &val) + { + d[floatReg] = val; + return NoFault; + } + + Fault setReg(int floatReg, const FloatReg &val, int width) + { + return setReg(floatReg, val); + } + + Fault setRegBits(int floatReg, const FloatRegBits &val) + { + q[floatReg] = val; + return NoFault; + } + + Fault setRegBits(int floatReg, const FloatRegBits &val, int width) + { + return setRegBits(floatReg, val); + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + + }; + + class MiscRegFile { + protected: + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + + public: + MiscReg readReg(int misc_reg); + + //These functions should be removed once the simplescalar cpu model + //has been replaced. + int getInstAsid(); + int getDataAsid(); + + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); + + Fault setReg(int misc_reg, const MiscReg &val); + + Fault setRegWithEffect(int misc_reg, const MiscReg &val, + ExecContext *xc); + + void copyMiscRegs(ExecContext *xc); + +#if FULL_SYSTEM + protected: + typedef uint64_t InternalProcReg; + + InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + + private: + InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc); + + Fault setIpr(int idx, InternalProcReg val, ExecContext *xc); + + void copyIprs(ExecContext *xc); +#endif + friend class RegFile; + }; + + struct RegFile { + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegs; // control register file + Addr pc; // program counter + Addr npc; // next-cycle program counter + Addr nnpc; + +#if FULL_SYSTEM + int intrflag; // interrupt flag + inline int instAsid() + { return miscRegs.getInstAsid(); } + inline int dataAsid() + { return miscRegs.getDataAsid(); } +#endif // FULL_SYSTEM + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + }; + +} // namespace AlphaISA + +#endif diff --git a/arch/alpha/registerfile.hh b/arch/alpha/registerfile.hh deleted file mode 100644 index 13288e087..000000000 --- a/arch/alpha/registerfile.hh +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_ALPHA_REGFILE_HH__ -#define __ARCH_ALPHA_REGFILE_HH__ - -#include "arch/alpha/types.hh" -#include "arch/alpha/constants.hh" -#include "sim/faults.hh" - -class Checkpoint; - -namespace AlphaISA -{ - - typedef IntReg IntRegFile[NumIntRegs]; - - class FloatRegFile - { - protected: - - union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - }; - - public: - - FloatReg readReg(int floatReg) - { - return d[floatReg]; - } - - FloatReg readReg(int floatReg, int width) - { - return readReg(floatReg); - } - - FloatRegBits readRegBits(int floatReg) - { - return q[floatReg]; - } - - FloatRegBits readRegBits(int floatReg, int width) - { - return readRegBits(floatReg); - } - - Fault setReg(int floatReg, const FloatReg &val) - { - d[floatReg] = val; - return NoFault; - } - - Fault setReg(int floatReg, const FloatReg &val, int width) - { - return setReg(floatReg, val); - } - - Fault setRegBits(int floatReg, const FloatRegBits &val) - { - q[floatReg] = val; - return NoFault; - } - - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) - { - return setRegBits(floatReg, val); - } - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - - }; - - class MiscRegFile { - protected: - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - - public: - MiscReg readReg(int misc_reg); - - //These functions should be removed once the simplescalar cpu model - //has been replaced. - int getInstAsid(); - int getDataAsid(); - - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); - - Fault setReg(int misc_reg, const MiscReg &val); - - Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc); - - void copyMiscRegs(ExecContext *xc); - -#if FULL_SYSTEM - protected: - typedef uint64_t InternalProcReg; - - InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs - - private: - InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc); - - Fault setIpr(int idx, InternalProcReg val, ExecContext *xc); - - void copyIprs(ExecContext *xc); -#endif - friend class RegFile; - }; - - struct RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; - -#if FULL_SYSTEM - int intrflag; // interrupt flag - inline int instAsid() - { return miscRegs.getInstAsid(); } - inline int dataAsid() - { return miscRegs.getDataAsid(); } -#endif // FULL_SYSTEM - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - }; - -} // namespace AlphaISA - -#endif diff --git a/arch/alpha/utility.hh b/arch/alpha/utility.hh index 92fb66c81..13bc01af4 100644 --- a/arch/alpha/utility.hh +++ b/arch/alpha/utility.hh @@ -32,7 +32,7 @@ #include "config/full_system.hh" #include "arch/alpha/types.hh" #include "arch/alpha/constants.hh" -#include "arch/alpha/registerfile.hh" +#include "arch/alpha/regfile.hh" #include "base/misc.hh" namespace AlphaISA -- cgit v1.2.3