From 4f430e9ab56443e822171b7881f4d50475dbaf25 Mon Sep 17 00:00:00 2001 From: Korey Sewell <ksewell@umich.edu> Date: Mon, 10 Apr 2006 12:23:17 -0400 Subject: Finally MIPS does hello world! arch/mips/isa/bitfields.isa: add RS_SRL bitfield ...these must be set to 0 for a SRL instruction arch/mips/isa/decoder.isa: Make unimplemented instructions Fail instead of just Warn Edits to SRA & SRAV instructions Implement CFC1 instructions Unaligned Memory Access Support (Maybe Not fully functional yet) Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions) arch/mips/isa/formats/branch.isa: Fix disassembly arch/mips/isa/formats/int.isa: Add sign extend Immediate and zero extend Immediate to Int class. Probably a bit unnecessary in the long run since these manipulations could be done in the actually instruction instead of keep a int value arch/mips/isa/formats/mem.isa: Comment/Remove out split-memory access code... revisit this after SimpleCPU works arch/mips/isa/formats/unimp.isa: Add inst2string function to Unimplemented panic. PRints out the instruction binary to help in debuggin arch/mips/isa/formats/unknown.isa: define inst2string function , use in unknown disassembly and panic function arch/mips/isa/operands.isa: Make "Mem" default to a unsigned word since this is MIPS32 arch/mips/isa_traits.hh: change return values to 32 instead of 64 arch/mips/linux_process.cc: assign some syscalls to the right functions cpu/static_inst.hh: more debug functions for MIPS (these will be move to the mips directory soon) mem/page_table.cc: mem/page_table.hh: toward a better implementation for unaligned memory access mem/request.hh: NO ALIGN FAULT flag added to support unaligned memory access sim/syscall_emul.cc: additional SyscallVerbose comments --HG-- extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c --- arch/mips/isa/formats/branch.isa | 2 +- arch/mips/isa/formats/int.isa | 16 +++--- arch/mips/isa/formats/mem.isa | 116 +++++--------------------------------- arch/mips/isa/formats/unimp.isa | 3 +- arch/mips/isa/formats/unknown.isa | 28 ++++++++- 5 files changed, 51 insertions(+), 114 deletions(-) (limited to 'arch/mips/isa/formats') diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index cb0f4ac9c..39db88c23 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -179,7 +179,7 @@ output decoder {{ ss << ","; } - Addr target = pc + 8 + disp; + Addr target = pc + 4 + disp; std::string str; if (symtab && symtab->findSymbol(target, str)) diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa index a47844bee..98e58f7f2 100644 --- a/arch/mips/isa/formats/int.isa +++ b/arch/mips/isa/formats/int.isa @@ -29,17 +29,19 @@ output header {{ { protected: - int32_t imm; + int16_t imm; + int32_t sextImm; + uint32_t zextImm; /// Constructor IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM) + MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), + sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) { //If Bit 15 is 1 then Sign Extend - int32_t temp = imm & 0x00008000; - + int32_t temp = sextImm & 0x00008000; if (temp > 0 && mnemonic != "lui") { - imm |= 0xFFFF0000; + sextImm |= 0xFFFF0000; } } @@ -99,9 +101,9 @@ output decoder {{ } if( mnemonic == "lui") - ccprintf(ss, "%08p ", imm); + ccprintf(ss, "%08p ", sextImm); else - ss << (int) imm; + ss << (int) sextImm; return ss.str(); } diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa index 8a07e63d4..a42976331 100644 --- a/arch/mips/isa/formats/mem.isa +++ b/arch/mips/isa/formats/mem.isa @@ -199,23 +199,8 @@ def template LoadMemAccExecute {{ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - EA = xc->getEA(); - - if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); - %(code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - + //Fill in Code for Out-of-Order CPUs return fault; } }}; @@ -251,18 +236,8 @@ def template LoadInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_src_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); - } - + //Fill in Code for Out-of-Order CPUs return fault; } }}; @@ -274,21 +249,7 @@ def template LoadCompleteAcc {{ Trace::InstRecord *traceData) const { Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_src_decl)s; - %(op_dest_decl)s; - - memcpy(&Mem, data, sizeof(Mem)); - - if (fault == NoFault) { - %(memacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - + //Fill in Code for Out-of-Order CPUs return fault; } }}; @@ -299,33 +260,8 @@ def template StoreMemAccExecute {{ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; Fault fault = NoFault; - uint64_t write_result = 0; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - EA = xc->getEA(); - - if (fault == NoFault) { - %(code)s; - } - - if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, &write_result); - if (traceData) { traceData->setData(Mem); } - } - - if (fault == NoFault) { - %(postacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - + //Fill in Code for Out-of-Order CPUs return fault; } }}; @@ -370,26 +306,8 @@ def template StoreInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; Fault fault = NoFault; - uint64_t write_result = 0; - - %(fp_enable_check)s; - %(op_src_decl)s; - %(op_dest_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - %(memacc_code)s; - } - - if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, &write_result); - if (traceData) { traceData->setData(Mem); } - } - + //Fill in Code for Out-of-Order CPUs return fault; } }}; @@ -401,21 +319,7 @@ def template StoreCompleteAcc {{ Trace::InstRecord *traceData) const { Fault fault = NoFault; - uint64_t write_result = 0; - - %(fp_enable_check)s; - %(op_dest_decl)s; - - memcpy(&write_result, data, sizeof(write_result)); - - if (fault == NoFault) { - %(postacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - + //Fill in Code for Out-of-Order CPUs return fault; } }}; @@ -448,6 +352,14 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, exec_template_base = 'Store') }}; +def format UnalignedStore(memacc_code, postacc_code, + ea_code = {{ EA = Rb + disp; }}, + mem_flags = [], inst_flags = []) {{ + (header_output, decoder_output, decode_block, exec_output) = \ + LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, + postacc_code, exec_template_base = 'Store') +}}; + //FP loads are offloaded to these formats for now ... def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }}, mem_flags = [], inst_flags = []) {{ diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa index 890cf8d1a..475a88752 100644 --- a/arch/mips/isa/formats/unimp.isa +++ b/arch/mips/isa/formats/unimp.isa @@ -110,7 +110,8 @@ output exec {{ Trace::InstRecord *traceData) const { panic("attempt to execute unimplemented instruction '%s' " - "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); + "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE, + inst2string(machInst)); return new UnimplementedOpcodeFault; } diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa index 47d166255..ba83c007e 100644 --- a/arch/mips/isa/formats/unknown.isa +++ b/arch/mips/isa/formats/unknown.isa @@ -26,12 +26,34 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +output header {{ + std::string inst2string(MachInst machInst); +}}; output decoder {{ + +std::string inst2string(MachInst machInst) +{ + string str = ""; + uint32_t mask = 0x80000000; + + for(int i=0; i < 32; i++) { + if ((machInst & mask) == 0) { + str += "0"; + } else { + str += "1"; + } + + mask = mask >> 1; + } + + return str; +} + std::string Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return csprintf("%-10s (inst 0x%x, opcode 0x%x)", - "unknown", machInst, OPCODE); + return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)", + "unknown", machInst, OPCODE, inst2string(machInst)); } }}; @@ -41,7 +63,7 @@ output exec {{ Trace::InstRecord *traceData) const { panic("attempt to execute unknown instruction " - "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); + "(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst)); return new UnimplementedOpcodeFault; } }}; -- cgit v1.2.3